CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5.17
DMA Slave Configuration Register
Register Name: DMA Slave Configuration Register
Offset: 90h
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Register Per: socket
Bit 25
Bit 24
Byte 3
Bit 23
Bit 22
Bit 21
DMA I/O Base Address (high)
R/W:00000000
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Byte 2
DMA I/O Base Address (high mid.)
R/W:00000000
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Byte 1
DMA I/O Base Address (low mid.)
Byte 0
Bit 7
Bit 6
Bit 5
DMA I/O Base Address (low)
R/W:0000
R/W:00000000
Bit 4
Bit 3
Non-Legacy
Extended
Addressing
R/W:0
Bit 2
Bit 1
Transfer Size
R/W:00
Bit 0
Channel
Enable
R/W:0
This is the DMA I/O base address for the DMA registers.
Bit 0 — Channel Enable
This bit, along with the DREQ Enable bits in Extension Control 1, enables the DMA channel.
When this bit is ‘0’, DMA operations are not allowed. If both of the DREQ Enable bits in Extension
Control 1 are ‘0’s, DMA operations are not allowed.
Bits 2:1 — Transfer Size
These bits define the size of the DMA transfer at the PC Card 16 (R2) socket.
Bit 2
Bit 1
Size of DMA Transfer at the PC Card 16 (R2) Socket
0
0
8-bit transfer at the PC Card
0
1
1
0
1
1
16-bit transfers at the PC Card
16-bit transfers at the PC Card a
16-bit transfers at the PC Card a
a These two settings are implemented for compatibility with current R2 conventions.
Bit 3 — Non-Legacy Extended Addressing
When this bit is set to ‘1’, it enables use of the DMA extended addressing.
Bits 31:4 — DMA I/O Base Address
These bits are used to define the I/O address where the DMA Operation registers can be located.
70
PCI CONFIGURATION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
Share Link: 
