CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
8.3 Power Control — PME _CXT
Register Name: Power Control — PME_CXT
I/O Index: 02h
Memory Offset: 802h
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Card Enable Compatibility Reserved VCC Power
Compatibility
VPP1 Power
R/W:0
R/W:0
R/W:0
R/W:0
R/W:00
R/W:00
NOTE: PME_CXT (PME Context) is a set of register bits that do not get reset or initialized if PME Enable is true
when the CL-PD6833 changes power states from D3 to D0 through a software PCI Bus Segment reset.
This register is write-protected by writes to the Event Force register. The register is not write protected
when a CV test completes. CV test can be started by a card insertion or by a write to bit 14 of the Event
Force register. Use either the Control register (see page 82) or this Power Control register to set card
power. Do not use both registers.
Table 8-2. Enabling of Socket Power Commands
Both CD1#
RST# Level and CD2# Are
Active (Low)
Low
X
High
X
High
No
High
Yes
Power Control
Register
VCC Power (Bit 4)
X
0
X
1
Interface Status
Register
(see page 92)
Card Power On (Bit 6)
VCC
Command
to Power
Device
VPP
Command to
Power Device
0
Inactive (high) Inactive (low)
0
Inactive (high) Inactive (low)
X
Inactive (high) Inactive (low)
Activated by bit A c t i va t e d b y
1
1 of the Misc bits 1 and 0 of
C o n t ro l 1
the Power
register
Control register
Table 8-3. Enabling of PC Card Output Signals to Socket
Both CD1# and
Power Control Register
RST# Level CD2# Are
Active (Low) VCC Power (Bit 4) Card Enable (Bit 7a)
Low
X
X
X
High
No
X
X
High
Yes
0
0
High
Yes
0
1
High
Yes
1
0
High
Yes
1
1
a This only applies to PC Card 16 (R2) cards.
State of the CL-PD6833 VCC
Command to Power Device
High-impedance
High-impedance
High-impedance
Enabled
High-impedance
Enabled
94
DEVICE CONTROL REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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