CL-PS6700-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS6700-VC-A' PDF : 48 Pages View PDF
Table 4-2. CL-PS6700 I/O Properties
CL-PS6700
Low-Power PC Card Controller
CL-PS7111 Interface: Multiplexed Address/Data Bus and Control
PCLK
H
I
sys
S
none
N
N
N
RESET_L
L
I
sys
A
none
N
N
N
PSLEEP_L
L
I
sys
A
none
N
N
N
PCE_L
L
I
sys
S
none
N
N
N
PTYPE
H
I
sys
S
none
N
N
N
PRDY
O
sys
S
none
T
A
A
INIT
H
I
sys
S
none
N
N
N
PDREQ_L
O
sys
S
none
T
PO
A
L
I
sys
S prog. PU N
N
N
PIRQ_L[0]
L
O
sys
A
none
T
A
A
PIRQ_L[1]
L
O
sys
A
none
T
A
A
MD[15:0]
O
sys
S
none
T
A
A
H
I
sys
S
none
N
N
N
PC Card Interface
PCM_WP
PCM_BVD[2:1]
H
I
pcm A prog. PU PI
N
PI
H
I
pcm A prog. PU PI
N
PIb
PCM_RDY
H
I
pcm A prog. PU PI
N
PI
PCM_WAIT_L
L
I
pcm A prog. PU PI
N
PI
PCM_CE_L[2:1]
L
O pcm A
none
T
A
T
PCM_REG_L
L
O pcm S
none
T
A
T
PCM_OE_L
L
O pcm S
none
T
A
T
PCM_WE_L
L
O pcm S
none
T
A
T
PCM_IORD_L
L
O pcm S
none
T
A
T
PCM_IOWR_L
L
O pcm S
none
T
A
T
PCM_RESET
L
O pcm S
none
T
A
T
PCM_A[25:0]
H
O pcm S
none
T
A
T
PCM_D[15:0]
O pcm S
none
T
A
T
H
I
pcm A
none
PI
PI
PI
PCM_CD_L[2:1]
Prog. I VDDhi S prog. PU PI prog. PI
N
PCM_VS[2:1]
O VDDhi S
none
T
A
T
Prog.
I VDDhi A prog. PU PI
N
PI
PCTL[2:0]
O VDDhi S
none
T
PO
A
Prog.
I VDDhi A prog. PU N
N
N
N
10
N
10
N
10
N
10
N
10
A
25
N
10
A
50
N
10
A
50
A
50
A
70
N
10
N
10
N
10
N
10
N
10
A
50
A
50
A
50
A
50
A
50
A
50
A
50
A
100
A
50
PI
10
N
50
A
50
N
10
A
50
N
10
a The Idle mode is entered and exited by writing the register bit Idle. In Idle mode most internal clocks are gated off, and only
the CL-PS6700 register access is supported. All CL-PS6700 inputs and outputs function normally.
b The PCM_BVD[1] input protection can be disabled during Card power-off.
32
REGISTERS
CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED
PRELIMINARY DATA BOOK v1.0
November 1997
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