CL-PS6700-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS6700-VC-A' PDF : 48 Pages View PDF
CL-PS6700
Low-Power PC Card Controller
5.1 Bus Timing — System Bus
Table 5-3. System Bus Timing Parameters
Symbol Parameter
t1a
PCE_L input setup
t1b
PCE_L input hold
t2a
PTYPE input setup
t2b
PTYPE input hold
t3a
MD bus address phase input setup
t3b
MD bus address phase input hold
t3c
MD bus data phase input setup
t3d
MD bus data phase input hold
t3e
PCLK high to MD bus output new data
t3f
PCE_L to MD bus output driven
t3g
PCLK high to MD bus output High-Z
t4a
PRDY input setup
t4b
PRDY input hold
t4c
RESET_L input high to PRDY input high
t4d
PCLK high to PRDY low
t4e
PCLK high to PRDY high
t4f
PCLK high to PRDY output driven
t4g
RESET_L low to PRDY output High-Z
t5a
External interrupt to PIRQ_L[1:0] low
t5b
PCLK high to PIRQ_L[1:0] low (internal interrupt sources)
t5c
PIRQ_L[1:0] low-to-high during Wake mode
t6a
PDREQ_L input setup
t6b
PDREQ_L input hold
t6c
PCLK to PDREQ_L high/low
t6d
PCLK high to PDREQ_L driven
t6e
PCLK high to PDREQ_L High-Z (when GPIO)
t6f
PCLK low to PDREQ_L High-Z (when PDREQ_L)
t18a
PCTL inputs setup
t18b
PCTL inputs hold
MIN
MAX
12
6
8
8
7
12
7
12
36
8
30
6
8
1 × TPCLK
25
25
25
35
40
45
8 × TPCLK
6
8
31
30
30
30
6
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED
November 1997
PRELIMINARY DATA BOOK v1.0
35
ELECTRICAL SPECIFICATIONS
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