CL-PS6700
Low-Power PC Card Controller
5.2 Bus Operations
PCLK
PCE_L
PTYPE
MD[15:0]
PRDY
PCM_A
PCM_REG_L
PCM_CE_L
PCM_D
PCM_WE_L
PCM_IOWR_L
ADDR PHASE
CYCLE 1
ADDR PHASE
CYCLE 2
DATA PHASE
CYCLE 1
DATA PHASE
CYCLE 2
t1a
t2a
t2b
t3a t3b
ADDR. HI
t4d
t3a t3b
ADDR. LO
t4e
t3c t3d
DATA MSB
t1b
t3c t3d
DATA LSB
t7a
t7b
Figure 5-1. Memory or Register Write
t8c
t9a
PCLK
PCE_L
PTYPE
MD[15:0]
PRDY
ADDR PHASE
CYCLE 1
ADDR PHASE
CYCLE 2
MD BUS
TURN-AROUND
DATA PHASE
CYCLE 1
DATA PHASE
CYCLE 2
t1a
t1b
t2a t2b
t3a t3b
ADDR. HI
t4d
t3a t3b
ADDR. LO
t4e
t3a
t3a
t3b
DATA MSB
DATA LSB
Figure 5-2. Register Read
CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED
38
ELECTRICAL SPECIFICATIONS
November 1997
PRELIMINARY DATA BOOK v1.0