CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
Pixel prescale
AC prescale
GSEN
GSMD
The pixel prescale field is a 6-bit field that sets the pixel rate prescale. The pixel rate
is derived from a 36.864-MHz clock and is calculated from the formula:
Pixel rate (MHz) = 36.864 / (pixel prescale + 1)
The pixel rate should be chosen to give a complete screen refresh frequency of
approximately 70 Hz to avoid flicker. Frequencies above 70 Hz should be avoided as
they consume additional power. The pixel prescale value can be expressed in terms
of the LCD size by the formula:
Pixel prescale = (526628 / Total pixels in display) − 1
The value should be rounded down to the nearest whole number. ‘0’ is illegal and will
result in no pixel clock.
For example: A 640 × 240 LCD, pixel prescale = 526628 / (640 × 240) − 1 = 2.428 (2)
This gives an actual pixel rate of 36.864E6 / 2 + 1 = 12.288 MHz
Which gives an actual refresh frequency of 12.288E6 / (640 × 240) = 80 Hz.
NOTE: As the CL2 low pulse time is doubled after every CL1 high pulse (see Figure 4-7),
this refresh frequency is only an approximation; the accurate formula is 12.288E6 /
((640 × 240) + 120) = 79.937 Hz.
The AC prescale field is a 5-bit number that sets LCD AC bias frequency. This fre-
quency is the required AC bias frequency for a given manufacturer’s LCD plate. This
frequency is derived from the frequency of the line clock (CL1). The ‘M’ signal toggles
after n+1 counts of the line clock (CL1) where n is the number programmed into the
AC prescale field. This number must be chosen to match the manufacturer’s recom-
mendation (normally 13), but must not be exactly divisible by the number of lines in
the display.
Grayscale enable bit. Setting this bit enables grayscale output to the LCD. When this
bit is cleared, each bit in the video map directly corresponds to a pixel in the display.
Grayscale mode bit. Clearing this bit sets the controller to 2 bits per pixel (4 gray-
scales). Setting sets the controller to 4 bits per pixel (15 grayscales).
3.2.19 TC1D — Timer Counter 1 Data Register
The Timer Counter 1 Data register is a 16-bit read/write register that sets and reads data to TC1. Any
value written is decremented on the next rising edge of the clock.
3.2.20 TC2D — Timer Counter 2 Data Register
The Timer Counter 2 Data register is a 16-bit read/write register that sets and reads data to TC2. Any
value written is decremented on the next rising edge of the clock.
3.2.21 RTCDR — Realtime Clock Data Register
The Realtime Clock Data register is a 32-bit read/write register that sets and reads the binary time in the
RTC. Any value written is incremented on the next rising edge of the 1-Hz clock. All bits in the Realtime
Clock Data register are only cleared by an active NPOR.
3.2.22 RTCMR — Realtime Clock Match Register
The Realtime Clock Match register is a 32-bit read/write register that sets and reads the binary match time
to RTC. Any value written is compared to the current binary time in the RTC, if they match it asserts the
RTCMI interrupt source.
May 1997
DATA BOOK v1.5
53
PROGRAMMING INTERFACE
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