CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
3.2.25 UARTDR — UART Data Register
The UARTDR register is an 11-bit read and 8-bit write register for all data transfers to or from the internal
UART.
Data written to this register is pushed onto the 16-byte data Tx holding FIFO if the FIFO is enabled; if not,
it is stored in a 1-byte holding register. This write initiates transmission from the UART.
The UART Data Read register comprises the 8-bit data byte received from the UART together with three
bits of error status. Data read from this register is popped from the 16-byte data Rx FIFO if the FIFO is
enabled, if not it is read from a 1-byte buffer register containing the last byte received by the UART. Data
received and error status is automatically pushed onto the Rx FIFO if it is enabled. The Rx FIFO is 10 bits
wide by 16 deep.
10
9
8
7
0
OVERR
PARERR
FRMERR
Rx data
FRMERR
PARERR
OVERR
UART framing error. This bit is set if the UART detected a framing error while receiv-
ing the associated data byte. Framing errors are caused by non-matching word
lengths or bit rates.
UART parity error. This bit is set if the UART detected a parity error while receiving
the data byte.
UART overrun error. This bit is set if more data is received by the UART and the FIFO
is full. The Overrun Error bit is not associated with any single character and so is not
stored in the FIFO, if this bit is set, the entire contents of the FIFO is invalid and should
be cleared. This error bit is cleared by reading the UARTDR register.
3.2.26 UBRLCR — UART Bit Rate and Line Control Register
The UART Bit Rate and Line Control register is a 19-bit read/write register. Writing to this register sets the
bit rate and mode of operation for the internal UART.
31 19 18
17 16
15
14
13
12
11
0
WRDLEN
FIFOEN
XSTOP
EVENPRT PRTEN
BREAK
Bit rate divisor
Bit rate divisor
This 12-bit field set the bit rate. The bit rate divider is fed by a clock frequency of
3.6864 MHz, it is then further divided internally by 16 to give the bit rate. The formula
to give the divisor value for any bit rate is: Divisor = (230400 / bit rate) - 1. A value of
‘0’ in this field is illegal. Table 3-12 shows some example bit rates with the corre-
sponding divisor value.
May 1997
DATA BOOK v1.5
55
PROGRAMMING INTERFACE
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