CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
Table 3-12. Internal UART Bit Rates
Divisor Value
1
2
3
5
11
15
23
95
191
2094
Bit Rate
115200
76800
57600
38400
19200
14400
9600
2400
1200
110
BREAK
PRTEN
Setting this bit drives the Tx output active (high) to generate a break.
Parity enable bit. Setting this bit enables parity detection and generation.
EVENPRT
Even parity bit. Setting this bit sets parity generation and checking to even parity,
clearing it sets odd parity. This bit has no effect if the PRTEN bit is clear.
XSTOP
Extra stop bit. Setting this bit causes the UART to transmit two stop bits after each
data byte, clearing it transmits one stop bit after each data byte.
FIFOEN
Set to enable FIFO buffering of Rx and Tx data. Clear to disable the FIFO, that is, set
its depth to one byte.
WRDLEN
This 2-bit field selects the word length according to Table 3-13.
Table 3-13. UART Word Length
WRDLEN
00
01
10
11
Word Length
5 bits
6 bits
7 bits
8 bits
3.2.27 PALLSW Least-Significant Word-LCD Palette Register
The least- and most-significant Word-LCD Palette registers make up a 64-bit read/write register, which
maps the logical pixel value to a physical grayscale level. The 64-bit register is made up of 16 × 4-bit nib-
bles, each nibble defines the grayscale level associated with the appropriate pixel value. If the LCD con-
troller is operating in two bits per pixel, only the lower four nibbles are valid D[15:0] in the least-significant
56
PROGRAMMING INTERFACE
May 1997
DATA BOOK v1.5
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