Bell 212A / V.22 Modem with Call Progress and DTMF
15
CMX644A Preliminary Information
4.3.2.8 RX PSK MODE Register ($E8)
(Bit 7)
CPBW SELECT
Bit 6
DE-SCRAMB UNLOCK
(Bit 5)
DE-SCRAMB ENABLE
(Bit 4)
EQUAL ER1 and ER0
(Bits 3 and 2)
ENABLE
(Bit 1)
HI/LO BAND
(Bit 0)
Reserved for future use. This bit should be set to ‘0’.
When this bit is set to ‘1’ the Call Progress Detector bandwidth is approximately
300Hz – 620Hz.
When this bit is set to ‘0’ the Call Progress Detector bandwidth is approximately
400Hz – 620Hz.
When this bit is set to ‘1’ the de-scrambler will check for sequences of 64
consecutive ones at its input and once detected it will invert the next output from
the de-scrambler. When this bit is set to ‘0’ the all ones detection is disabled - it
should be set as such until the handshaking sequence is complete.
When this bit is set to ‘1’ the Rx data is passed through the de-scrambler. When
it is set to ‘0’ the de-scrambler is bypassed.
These 2 bits control the level of equalization applied to the received signal
according to Table 19.
See Figure 8 and Figure 9 for the typical equalizer responses. The equalizer is
automatically powersaved when ET1 and ET0 are set to “no equalization” (‘0’,
‘0’).
When this bit is set to ‘1’ the PSK receiver is enabled. When it is set to ‘0’ the
receiver is disabled. Associated flags are only set when this bit is ‘1’.
This bit determines whether the received PSK signal should be filtered and
derived from the low channel (900Hz - 1500Hz) or the high channel (2100Hz -
2700Hz). When this bit is set to ‘0’ the low channel is selected. When it is set to
‘1’ the high channel is selected.
Table 18: RX PSK MODE Register ($E8)
ER1 (Bit 3)
0
0
1
1
ER0 (Bit 2)
0
1
0
1
Receiver Equalization
no equalization
Low
Medium
High
Table 19: EQUAL ER1 and ER2
2000 MX-COM, Inc.
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