Bell 212A / V.22 Modem with Call Progress and DTMF
17
CMX644A Preliminary Information
4.3.3.1 RX DATA BYTE Register ($EA)
This register contains the last byte of data received. It is updated every 8 bits at the same time as the RX
DATA READY flag is set. The RX DATA BYTE register is double buffered, thus giving the user up to 8 bit
periods to read the data before it is overwritten by the next byte. Each received phase change is decoded
into 2 bits (dibits). The incoming dibits fill this register starting at the most significant end (Bits 7 and 6).
Symbol values
00
01
11
10
Phase change
+90°
0°
+270°
+180°
Table 22: RX DATA BYTE Register ($EA)
Note: The left-hand digit of the dibit will be the more significant of the 2 bits when located in this register.
4.3.3.2 TONES DETECT Register ($EC)
This register provides information as to the presence or absence of various signaling conditions detected by
the receiver. A logic ‘1’ indicates that the signaling condition is present; a logic ‘0’ indicates that it is absent.
(Bit 7)
RING DETECT LEVEL
(Bit 6)
CALL PRGRSS DETECT
(Bit 5)
CARRIER DETECT
(Bit 4)
ANSWER DETECT
(Bit 3)
Bits 2 and 1
UNSCRAM MARK DETECT
(Bit 0)
This bit will be set to ‘1’.
Indicates the status of the Ring/Line Polarity Reversal Detector circuit. The
logic level of this bit represents the level of the internal ‘RING DETECT’ node
(See Figure 1).
Indicates the detection of call progress tones in the selected band. (300Hz to
620Hz or 400Hz to 620Hz).
Indicates the detection of a carrier in the received channel.
Indicates the detection of an Answer Tone of 2100Hz or 2225Hz.
These bits will be set to ‘0’.
Indicates the detection of unscrambled binary one in the received data for a
period of time of 160ms.
Table 23: TONES DETECT Register ($EC)
Note: DETECT bits 5, 4 and 3 are mutually exclusive and are enabled by the setting of the DETECT DET1 or
DET0 bits (SET-UP Registers Bits 5 and 4). All the DETECT bits in the TONES DETECT register - except for
RING DETECT (Bit 6) - require the RX PSK MODE register ENABLE bit to be set to ‘1’.
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