Bell 212A / V.22 Modem with Call Progress and DTMF
18
CMX644A Preliminary Information
4.3.3.3 FLAGS Register ($EF)
The flags register is used to indicate when the device requires attention. When a flag becomes set to ‘1’ and
its corresponding mask bit is ‘1’ then an interrupt ( IRQ ) will be generated. Immediately after the flags register
has been read, all the bits will be reset to ‘0’ and consequently any interrupt will be cleared.
RX PARITY flag
(Bit 7)
RING DETECT CHANGE
flag (Bit 6)
DETECT flag
(Bit 5)
RX DATA OVERFLOW
flag (Bit 4)
RX DATA READY flag
(Bit 3)
TX DATA UNDERFLOW
flag (Bit 2)
TX DATA READY flag
(Bit 1)
UNSCRAM MARK flag
(Bit 0)
When this bit is ‘1’ the received parity is in error. When this bit is ‘0’ the
received parity is correct.
When RING DETECT (TONES DETECT Register, Bit 6) changes state, this
bit will be set to ‘1’.
When any of the following bits - CALL PRGRSS DETECT, CARRIER
DETECT or ANSWER DETECT (TONES DETECT Register Bits 5, 4, 3) -
change state, this bit will be set to ‘1’.
If received data is not read out of the device within the 8-bit window of RX
DATA READY going high, then this bit will be set to ‘1’ to indicate an error
condition.
When a full byte of data is received and is available in the RX DATA BYTE
register, this bit will be set to ‘1’. There is then an 8-bit window during which
the RX DATA BYTE register must be read.
If data is not loaded into the TX DATA BYTE register within the 8-bit window
of TX DATA READY going high, then this bit will be set to ‘1’ to indicate an
error condition.
When the Tx data buffer is ready to receive a new byte of data, this bit will be
set to ‘1’. There is then an 8-bit window for the loading of the TX DATA BYTE
register.
When the UNSCRAM MARK DETECT bit (TONES DETECT Register Bit 0)
changes state, this bit will be set to ‘1’.
Table 24: FLAGS Register ($EF)
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