D950-CORE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'D950-CORE' PDF : 89 Pages View PDF
D950-Core
4.4.2 Registers
PCDR
The Port Control Direction register defines the data direction of each port pin. After reset,
PCDR default value is 0 (Port pins are configured as inputs).
15 14 13 12 11 10 9
-
-
-
-
-
-
-
876543210
- P7D P6D P5D P4D P3D P2D P1D P0D
PiD: Port pin direction
0: Input port pin (def.)
1: Output port pin
- : for bits 8 to 15 indicates RESERVED (read: undefined, write: don’t care)
PCSR
The Port Control Sensitivity register defines sensitivity of each port pin. After reset, PCSR
default value is 0 (Port pins are configured as level-sensitive).
15 14 13 12 11 10 9
-
-
-
-
-
-
-
876543210
- P7S P6S P5S P4S P3S P2S P1S P0S
PiS: Port pin sensitivity
0: Level sensitive (def.)
1: Edge sensitive
- : for bits 8 to 15 indicates RESERVED (read: undefined, write: don’t care)
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