D950-CORE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'D950-CORE' PDF : 89 Pages View PDF
D950-Core
1: Data contained in R0 and R1 is long 32-bit data (the 16 MSB’s in R1, the 16 LSB’s
in R0)
LL: Left side long data
0: Normal 16-bit data mode (def.)
1: Data contained in L0 and L1 is long 32-bit data (the 16 MSB’s in L1, the 16 LSB’s in
L0)
4.5.2 CCR: Condition Code Register
CCR is a 16-bit register shared by both the DCU (bits 0 to 12) and the PCU (bits 14 and 15).
This register is affected each time an ALU operation occurs, and gives information on the last
result stored in A0 or A1 accumulator.
After reset, CCR default value is 0.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSP1 LSP0 - TST C31 NQ CS PAR MN N EXT MOVF OVF Z
C
S
PCU
-
DCU
LSP1/LSP0 Loop Stack Pointer
00: No loop / Bank 1 (def.)
01: Loop level 1 / Bank 1
10: Loop level 2 / Bank 2
11: Loop level 3 / Bank 3
TST: Result of the test instructions in bit manipulation or last bit shifted out in pure shift
operations
C31: Carry value generated out of bit 31 during the last ALU operation (always loaded
except for DMULT instruction)
NQ: 1’s complement of next quotient bit (only affected by DIVS and DIVQ instructions)
CS: Compared sign updated by CMPS instruction as the XOR of the two ALU operand
signs (bit 31) (used also by DIVS, RESQ and RESR instructions)
PAR: Parity of the last ALU result.
0: Bit 16 of the last 40-bit ALU result is 0 (def.)
1: Bit 16 of the last 40-bit ALU result is 1
MN: Memorized normalized
0: Reset when tested by a conditional instruction (def.)
1: Set when ALU result is normalized
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