D950-CORE View Datasheet(PDF) - STMicroelectronics
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MFG CO.
'D950-CORE' PDF : 89 Pages View PDF
D950-Core
5 SOFTWARE ARCHITECTURE
5.1 Introduction
Instruction execution is performed in a 3-stage pipeline: fetch/decode/execute. While
instruction n is executed, instruction n+1 is decoded and instruction n+2 is fetched. The
instruction cycle period is twice the CLKIN period. According to the number of words used,
D950-Core instructions can be of two types: one word intructions or extension word
instructions.
One Word Instructions:
Most of D950-Core instructions are one cycle instructions:
• All arithmetic and logic instructions with or without parallel data moves,
excepted instructions performing double precision multiplication and bit manip-
ulations.
• Register to register data move.
• Memory to register indirect data move.
The following are multiple cycle instructions:
• Double precision MAC (two cycles).
• Indirect indexed register move (two cycles).
• Indirect indexed register to stack move (two cycles).
• Register to Program memory transfer (four cycles).
Instructions causing a program flow change (RTS, RTI, SWI, RESET, BREAK, CONTINUE)
are executed in one to three cycles.
Extension Word Instructions:
One program memory word is fetched at each cycle, therefore, if an instruction needs
extension words, they are fetched during the cycles following the first fetch. Execution of the
instruction starts two cycles after its first fetch cycle.
• Memory to register data move in direct addressing mode (2-words/2-cycles)
(second word = address value).
• Immediate register load (2-words/2-cycles) (second word = register value).
• Repeat block up to 511 times (2-words/2-cycles) (second word = LE).
• Repeat single up to 216-1 times (2-words/2-cycles) (second word = LC).
• Repeat block computed (2-words/2-cycles) (second word = LC).
• Bit manipulations (2-words/2-cycles) (second word = mask).
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