DM9008C View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
'DM9008C' PDF : 52 Pages View PDF
MRCMDX
MRCMDX1
MRCMD
MRRL
MRRH
MWCMDX
MWCMD
MWRL
MWRH
TXPLL
TXPLH
ISR
IMR
DM9008C
Ethernet Controller with General Processor Interface
Memory Data Pre-Fetch Read Command Without Address F0H
XXH
Increment Register
Memory Data Read Command With Address Increment F1H
XXH
Register
Memory Data Read Command With Address Increment F2H
XXH
Register
Memory Data Read_ address Register Low Byte
F4H
00H
Memory Data Read_ address Register High Byte
F5H
00H
Memory Data Write Command Without Address Increment F6H
XXH
Register
Memory Data Write Command With Address Increment F8H
XXH
Register
Memory Data Write_ address Register Low Byte
FAH
00H
Memory Data Write _ address Register High Byte
FBH
00H
TX Packet Length Low Byte Register
FCH
XXH
TX Packet Length High Byte Register
FDH
XXH
Interrupt Status Register
FEH
00H
Interrupt Mask Register
FFH
00H
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where：
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
P = power on reset default value
S = software reset default value
E = default value from EEPROM
T = default value from strap pin
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
Preliminary
14
Version: DM9008C-13-DS-P01
January 15, 2008
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