DM9008C View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
'DM9008C' PDF : 52 Pages View PDF
DM9008C
Ethernet Controller with General Processor Interface
6.7 RX Status Register ( 06H )
Bit
Name
Default
7
RF
PS0,RO
6
MF
PS0,RO
5
LCS
PS0,RO
4
RWTO PS0,RO
3
PLE
PS0,RO
2
AE
PS0,RO
1
CE
PS0,RO
0
FOE
PS0,RO
Description
Runt Frame
It is set to indicate that the size of the received frame is smaller than 64 bytes
Multicast Frame
It is set to indicate that the received frame has a multicast address
Late Collision Seen
It is set to indicate that a late collision is found during the frame reception
Receive Watchdog Time-Out
It is set to indicate that it receives more than 2048 bytes
Physical Layer Error
It is set to indicate that a physical layer error is found during the frame reception
Alignment Error
It is set to indicate that the received frame ends with a non-byte boundary
CRC Error
It is set to indicate that the received frame ends with a CRC error
FIFO Overflow Error
It is set to indicate that a FIFO overflow error happens during the frame reception
6.8 Receive Overflow Counter Register ( 07H )
Bit
Name
Default
Description
7
RXFU
PS0,R/C
Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition
6:0
ROC
PS0,R/C
Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO overflow
6.9 Back Pressure Threshold Register (08H)
Bit
Name
Default
Description
Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern
7:4
BPHW
PS3, RW
when RX SRAM free space is lower than this threshold value
The default is 3K-byte free space. Please do not exceed SRAM size
(1 unit=1K bytes)
Jam Pattern Time. Default is 200us
bit3 bit2 bit1 bit0 time
0000
5us
0001
10us
0010
15us
0011
25us
0100
50us
0 1 0 1 100us
3:0
JPT
PS7, RW
0110
0111
150us
200us
1 0 0 0 250us
1 0 0 1 300us
1 0 1 0 350us
1 0 1 1 400us
1 1 0 0 450us
1101
1110
500us
550us
1 1 1 1 600us
Preliminary
17
Version: DM9008C-13-DS-P01
January 15, 2008
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