DM9008C View Datasheet(PDF) - Davicom Semiconductor, Inc.

Part Name

Description

MFG CO.

DM9008C

Ethernet Controller with General Processor Interface

Davicom Semiconductor, Inc. 

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DM9008C

Ethernet Controller with General Processor Interface

6.1 Network Control Register (00H)

Bit

Name

Default

Description

7 RESERVED P0,RW Reserved

6

WAKEEN

When set, it enables the wakeup function. Clearing this bit will also clears all

P0,RW wakeup event status

This bit will not be affected after a software reset

5 RESERVED 0,RO Reserved

4

FCOL

PS0,RW Force Collision Mode, used for testing

3

FDX

PS0,RO Full-Duplex Mode of the internal PHY.

2:1

LBK

PS00,

RW

Loop-back Mode

Bit 2 1

0 0 Normal

0 1 MAC Internal Loop-back

1 0 Internal PHY 100M mode digital Loop-back

1 1 (Reserved)

0

RST

P0,RW Software reset and auto clear after 10us

6.2 Network Status Register (01H)

Bit

Name

Default

Description

7 RESERVED X,RO Reserved

6

LINKST

X,RO Link Status 0:link failed 1:link OK,

5

WAKEST

P0, Wakeup Event Status. Clears by read or write 1 (work in 8-bit mode)

RW/C1 This bit will not be affected after software reset

4 RESERVED 0,RO Reserved

3

TX2END

PS0, TX Packet 2 Complete Status. Clears by read or write 1

RW/C1 Transmit completion of packet index 2

2

TX1END

PS0, TX Packet 1 Complete status. Clears by read or write 1

RW/C1 Transmit completion of packet index 1

1

RXOV

PS0,RO RX FIFO Overflow

0 RESERVED 0,RO Reserved

6.3 TX Control Register (02H)

Bit

Name

Default

7 RESERVED 0,RO

6

TJDIS

PS0,RW

5

EXCECM PS0,RW

4 PAD_DIS2 PS0,RW

3 CRC_DIS2 PS0,RW

2 PAD_DIS1 PS0,RW

1 CRC_DIS1 PS0,RW

0

TXREQ

PS0,RW

Description

Reserved

Transmit Jabber Disable

When set, the transmit Jabber Timer (2048 bytes) is disabled. Otherwise it is

Enable

Excessive Collision Mode Control : 0:aborts this packet when excessive collision

counts more than 15, 1: still tries to transmit this packet

PAD Appends Disable for Packet Index 2

CRC Appends Disable for Packet Index 2

PAD Appends Disable for Packet Index 1

CRC Appends Disable for Packet Index 1

TX Request. Auto clears after sending completely

Preliminary

15

Version: DM9008C-13-DS-P01

January 15, 2008

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