DM9008C View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
'DM9008C' PDF : 52 Pages View PDF
DM9008C
Ethernet Controller with General Processor Interface
6.10 Flow Control Threshold Register ( 09H )
Bit
Name
Default
Description
RX FIFO High Water Overflow Threshold
Send a pause packet with pause_ time=FFFFH when the RX RAM free space is
7:4
HWOT PS3, RW less than this value., If this value is zero, its means no free RX SRAM space. The
default value is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K
bytes)
RX FIFO Low Water Overflow Threshold
Send a pause packet with pause time=0000 when RX SRAM free space is larger
3:0
LWOT
PS8, RW
than this value. This pause packet is enabled after the high water pause packet is
transmitted. The default SRAM free space is 8K-byte. Please do not exceed SRAM
size
(1 unit=1K bytes)
6.11 RX/TX Flow Control Register ( 0AH )
Bit
Name
Default
Description
TX Pause Packet
7
TXP0
PS0,RW Auto clears after pause packet transmission completion. Set to TX pause packet
with time = 0000h
TX Pause packet
6
TXPF
PS0,RW Auto clears after pause packet transmission completion. Set to TX pause packet
with time = FFFFH
5
TXPEN
PS0,RW
Force TX Pause Packet Enable
Enables the pause packet for high/low water threshold control
Back Pressure Mode
4
BKPA
PS0,RW This mode is for half duplex mode only. It generates a jam pattern when any
packet comes and RX SRAM is over BPHW of register 8.
Back Pressure Mode
3
BKPM
PS0,RW This mode is for half duplex mode only. It generates a jam pattern when a packet’s
DA matches and RX SRAM is over BPHW of register 8.
2
RXPS
PS0,R/C RX Pause Packet Status, latch and read clearly
1
RXPCS PS0,RO RX Pause Packet Current Status
0
FLCE
PS0,RW
Flow Control Enable
Set to enable the flow control mode (i.e. can disable DM9008C TX function)
6.12 EEPROM & PHY Control Register ( 0BH )
Bit
Name
Default
Description
7:6 RESERVED 0,RO Reserved
5
REEP
P0,RW Reload EEPROM. Driver needs to clear it up after the operation completes
4
WEP
P0,RW Write EEPROM Enable
3
EPOS
P0,RW
EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
2
ERPRR
P0,RW
EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
1
ERPRW
P0,RW
EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.
0
ERRE
P0,RO
EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress
Preliminary
18
Version: DM9008C-13-DS-P01
January 15, 2008
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