DM9008C View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
'DM9008C' PDF : 52 Pages View PDF
DM9008C
Ethernet Controller with General Processor Interface
6.28 Early Transmit Control/Status Register ( 30H )
Bit
Name
Default
Description
7
ETE
PS0, RW
Early Transmit Enable
Enable bits[2:0]
6
ETS2
PS0,RO Early Transmit Status II
5
ETS1
PS0,RO Early Transmit Status I
4~2 RESERVED 000,RO Reserved
Early Transmit Threshold
Start transmit when data write to TX FIFO reach the byte-count threshold
Bit-1 bit-0 threshold
1~0
ETT
PS0,RW ----- ---- -------------
0 0 : 12.5%
0 1 : 25%
1 0 : 50%
1 1 : 75%
6.29 Check Sum Control Register ( 31H )
Bit
Name
Default
Description
7~3 RESERVED 0,RO Reserved
2
UDPCSE PS0,RW UDP CheckSum Generation Enable
1
TCPCSE PS0,RW TCP CheckSum Generation Enable
0
IPCSE
PS0,RW IP CheckSum Generation Enable
6.30 Receive Check Sum Status Register ( 32H )
Bit
Name
Default
Description
7
UDPS
PS0,RO
UDP CheckSum Status
1: checksum fail, if UDP packet
6
TCPS
PS0,RO
TCP CheckSum Status
1: checksum fail, if TCP packet
5
IPS
PS0,RO
IP CheckSum Status
1: checksum fail, if IP packet
4
UDPP
PS0,RO UDP Packet
3
TCPP
PS0,RO TCP Packet
2
IPP
PS0,RO IP Packet
Receive CheckSum Checking Enable
1
RCSEN
PS0,RW When set, the checksum status (bit 7~2) will be stored in packet’s first byte(bit
7~2) of status header respectively.
0
DCSE
PS0,RW
Discard CheckSum Error Packet
When set, if IP/TCP/UDP checksum field is error, this packet will be discarded.
Preliminary
22
Version: DM9008C-13-DS-P01
January 15, 2008
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