DM9008C View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
'DM9008C' PDF : 52 Pages View PDF
DM9008C
Ethernet Controller with General Processor Interface
8.1 Basic Mode Control Register (BMCR) - 00
Bit
Bit Name
Default
Description
0.15
Reset
0, RW/SC Reset
1=Software reset
0=Normal operation
This bit sets the status and controls the PHY registers to their default
states. This bit, which is self-clearing, will keep returning a value of
one until the reset process is completed
0.14
Loop-back
0, RW Loop-back
Loop-back control register
1 = Loop-back enabled
0 = Normal operation
0.13 Speed selection 1, RW Speed Select
1 = 100Mbps (The DM9008C only support 100M Fiber mode).
0 = 10Mbps
Link speed may be selected either by this bit or by auto-negotiation.
When auto-negotiation is enabled and bit 12 is set, this bit will return
auto-negotiation selected medium type
0.12 Auto-negotiation 1, RW Auto-negotiation Enable
enable
1 = Auto-negotiation is enabled, bit 8 and 13 will be in
auto-negotiation status
0.11
Power down
0, RW Power Down
While in the power-down state, the PHY should respond to
management transactions.
1=Power down
0=Normal operation
0.10
Isolate
0,RW Isolate
Force to 0 in application.
0.9
Restart
0,RW/SC Restart Auto-negotiation
Auto-negotiation
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this register
cleared), this bit has no function and it should be cleared. This bit is
self-clearing and it will keep returning to a value of 1 until
auto-negotiation is initiated by the DM9008C. The operation of the
auto-negotiation process will not be affected by the management
entity that clears this bit
0 = Normal operation
0.8
Duplex mode
1,RW Duplex Mode
1 = Full duplex operation. Duplex selection is allowed when
Auto-negotiation is disabled (bit 12 of this register is cleared). With
auto-negotiation enabled, this bit reflects the duplex capability
selected by auto-negotiation
0 = Normal operation
0.7
Collision test
0,RW Collision Test
1 = Collision test enabled. When set, this bit will cause the collision
asserted during the transmit period.
0 = Normal operation
0.6-0.0
Reserved
0,RO Reserved
Read as 0, ignore on write
Preliminary
28
Version: DM9008C-13-DS-P01
January 15, 2008
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