DM9008C View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
'DM9008C' PDF : 52 Pages View PDF
DM9008C
Ethernet Controller with General Processor Interface
6.44 Interrupt Status Register (FEH)
Bit
Name
Default
7
IOMODE
T0, RO
6 RESERVED
RO
5
LNKCHG PS0,RW/C1
4
UDRUN
PS0,RW/C1
3
ROO
PS0,RW/C1
2
ROS
PS0,RW/C1
1
PT
PS0,RW/C1
0
PR
PS0,RW/C1
Description
0 : 16-bit mode
1: 8-bit mode
Reserved
Link Status Change
Transmit Under-run
Receive Overflow Counter Overflow
Receive Overflow
Packet Transmitted
Packet Received
6.45 Interrupt Mask Register (FFH)
Bit
Name
Default
7
PAR
PS0,RW
6 RESERVED
RO
5
LNKCHGI
PS0,RW
4
UDRUNI
PS0,RW
3
ROOI
PS0,RW
2
ROI
PS0,RW
1
PTI
PS0,RW
0
PRI
PS0,RW
Description
Enable the SRAM read/write pointer to automatically return to the start
address when pointer addresses are over the SRAM size. Driver needs to
set. When driver sets this bit, REG_F5 will set to 0Ch automatically
Reserved
Enable Link Status Change Interrupt
Enable Transmit Under-run Interrupt
Enable Receive Overflow Counter Overflow Interrupt
Enable Receive Overflow Interrupt
Enable Packet Transmitted Interrupt
Enable Packet Received Interrupt
Preliminary
25
Version: DM9008C-13-DS-P01
January 15, 2008
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