DM9008C View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
'DM9008C' PDF : 52 Pages View PDF
DM9008C
Ethernet Controller with General Processor Interface
6.35 Resume System Clock Control Register ( 51H )
When the INDEX port set to 51H, the internal system clock is turn ON.
6.36 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H)
Bit
Name
Default
Description
Read data from RX SRAM. After the read of this command, the read pointer of
7:0 MRCMDX X,RO internal SRAM is unchanged. And the DM9008C starts to pre-fetch the SRAM data
to internal data buffers.
6.37 Memory Data Read Command without Address Increment Register (F1H)
Bit
Name
Default
Description
7:0 MRCMDX1
X,RO
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged
6.38 Memory Data Read Command with Address Increment Register (F2H)
Bit
Name
Default
Description
7:0 MRCMD
X,RO
Read data from RX SRAM. After the read of this command, the read pointer is
increased by 1or 2 depends on the operator mode (8-bit or16-bit respectively)
6.39 Memory Data Read address Register (F4H~F5H)
Bit
Name
Default
Description
7:0 MDRAH PS0,RW Memory Data Read_ addresses High Byte. It will be set to 0Ch, when IMR bit7 =1
7:0 MDRAL PS0,RW Memory Data Read_ address Low Byte
6.40 Memory Data Write Command without Address Increment Register (F6H)
Bit
Name
Default
Description
7:0
MWCMDX
X,WO
Write data to TX SRAM. After the write of this command, the write pointer is
unchanged
6.41 Memory data write command with address increment Register (F8H)
Bit
Name
Default
Description
Write Data to TX SRAM
7:0 MWCMD X,WO After the write of this command, the write pointer is increased by 1 or 2, depends on
the operator mode. (8-bit or 16-bit respectively)
6.42 Memory data write address Register (FAH~FBH)
Bit
Name
Default
Description
7:0 MDWAH PS0,RW Memory Data Write_ address High Byte
7:0 MDWAL PS0,RW Memory Data Write_ address Low Byte
6.43 TX Packet Length Register (FCH~FDH)
Bit
Name
Default
7:0
TXPLH
X,R/W TX Packet Length High byte
7:0
TXPLL
X,,R/W TX Packet Length Low byte
Description
Preliminary
24
Version: DM9008C-13-DS-P01
January 15, 2008
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