DM9008C View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
'DM9008C' PDF : 52 Pages View PDF
DM9008C
Ethernet Controller with General Processor Interface
6.31 LED Pin Control Register ( 34H )
Bit
Name
Default
Description
7:2 Reserved PS0,RO Reserved
LED act as General Purpose signals in 16-bit mode
1
GPIO
P0,RW 1: Pin 38/39 (LED2/1) act as the general purpose pins that are controlled by
registers 1Eh bit 2/1 and 1Fh bit 2/1 respectively.
LED act as SMI signals in 16-bit mode
1: Pin 38/39 (LED2/1) act as the MII Management Interface mode.
0
MII
P0,RW
In this mode, the LED1 act as data (MDIO) signal and the LED2 act as sourced
clock (MDC) signal.
These two pin are controlled by registers 0Bh,0Ch, and 0Dh.
6.32 Processor Bus Control Register ( 38H )
Bit
Name
Default
Description
7
Reserved P0,RW Reserved
Data Bus Current Driving/Sinking Capability
00: 2mA (default)
6:5
CURR
P00,RW 01: 4mA
10: 6mA
11: 8mA
4
Reserved P0,RW Reserved
3
EST
P0,RW
Enable Schmitt Trigger
1: Pin 35/36/37 (IOR/IOW/CS#) have Schmitt trigger capability.
2
Reserved P0,RW Reserved
1
IOW_SPIKE
P0,RW
Eliminate IOW spike
1: eliminate about 2ns IOW spike
0
IOR_SPIKE
P1,RW
Eliminate IOR spike
1: eliminate about 2ns IOR spike
6.33 INT Pin Control Register ( 39H )
Bit
Name
Default
7:2 Reserved PS0,RO Reserved
INT Pin Output Type Control
1
INT_TYPE PET0,RW 1: INT Open-Collector output
0: INT direct output
INT Pin Polarity Control
0
INT_POL PET0,RW 1: INT active low
0: INT active high
Description
6.34 System Clock Turn ON Control Register ( 50H )
Bit
Name
Default
Description
7:1 Reserved
-
Reserved
Stop Internal System Clock
0
DIS_CLK
P0,W 1: internal system clock turn off, internal PHYceiver also power down
0: internal system clock is ON
Preliminary
23
Version: DM9008C-13-DS-P01
January 15, 2008
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