DM9010 View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
DM9010
Davicom Semiconductor, Inc.
'DM9010' PDF : 61 Pages View PDF
35
TXVDD25
5.7 Miscellaneous
16,17,18, TEST1~TEST4
19
DM9010
Single Chip Ethernet Controller with General Processor Interface
P Internal regulator 2.5V output for TP TX
I Operation Mode
Test 1, 2, 3, 4 = (1, 1, 0, 0) in normal application
48
TEST5
68,69,70,
71,
74,75,77
GP0~6
78
LINK_O
79
WAKE
80
PW_RST#
36
NC
I,PD Internal system clock source
0: use internal 50MHz clock *(Suggestion)
1: use CLK20MO pin
I/O,PD General I/O Ports
Registers GPCR and GPR can program these pins
The GPIO0 is an output mode, and output data high at default is to power
down internal PHY and other external MII device
GP1~3 defaults are input ports, GP 0,4~6 force to output ports.
O,PD Cable Link Status Output. Active High
This pin is also used as a strap pin to define whether the MII interface is a
reversed MII interface (pulled high) or a normal MII interface (not pulled
high). This pin has a pulled down resistor about 60k ohm internally.
O,PD Issue a wake up signal when wake up event happens
This pin has a pulled down resistor about 60k ohm internally.
I Power on Reset
Active low signal to initiate the DM9010
The DM9010 is ready after 5us when this pin deasserted
NC NC
5.8 Power Pins
5,20,55,
DVDD
72,90,73
15,23,42,
GND
58,63,81,
99,76
P Digital VDD
P Digital GND
5.9 strap pins table
1: pull-high 1K~10K, 0: floating.
Pin No.
Pin Name Description
57
65
79
67
52,51,
50
78
MDC
EEDO
WAKE
EECS
TXD[2:0]
LINK_O
Polarity of INT
1: INT pin low active;
0: INT pin high active
DATA Bus Width
WAKE EEDO data width
0
0
16-bit
0
1
32-bit
1
0
8-bit
1
1
reserved
LED Mode
When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0
IO base address. (not available in 32-bit mode)
IO base = (strap pin value of TXD [2:0]) * 10H + 300H
Reverse MII
Preliminary
14
Version: DM9010-17--DS-P04
Jan. 18, 2006
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