DM9010 View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
DM9010
Davicom Semiconductor, Inc.
'DM9010' PDF : 61 Pages View PDF
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
DM9010
Single Chip Ethernet Controller with General Processor Interface
WO = Write only
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
6.1 Network Control Register (00H)
Bit
Name
Default
Description
7
EXT_PHY PH0,RW Selects external PHY when set. Selects Internal PHY when clear. This bit will not
be affected after software reset
6
WAKEEN P0,RW Wakeup Event Enable
When set, it enables the wakeup function. Clearing this bit will also clears all
wakeup event status
This bit will not be affected after a software reset
5 RESERVED 0,RO Reserved
4
FCOL PHS0,RW Force Collision Mode, used for testing
3
FDX
PHS0,RW Full-Duplex Mode. Read only on Internal PHY mode. R/W on External PHY mode
2:1
LBK
PHS00, Loopback Mode
RW Bit 2 1
0 0 Normal
0 1 MAC Internal Loopback
1 0 Internal PHY 100M mode digital Loopback
1 1 (Reserved)
0
RST
PH0,RW Software reset and auto clear after 10us
6.2 Network Status Register (01H)
Bit
Name
Default
Description
7
SPEED
X,RO Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has no
meaning when LINKST=0
6
LINKST
X,RO Link Status 0:link failed 1:link OK, when Internal PHY is used
5
WAKEST
P0, Wakeup Event Status. Clears by read or write 1
RW/C1 This bit will not be affected after software reset
4 RESERVED 0,RO Reserved
3
TX2END PHS0, TX Packet 2 Complete Status. Clears by read or write 1
RW/C1 Transmit completion of packet index 2
2
TX1END PHS0, TX Packet 1 Complete status. Clears by read or write 1
RW/C1 Transmit completion of packet index 1
1
RXOV PHS0,RO RX FIFO Overflow
0 RESERVED 0,RO Reserved
6.3 TX Control Register (02H)
Bit
Name
Default
7 RESERVED 0,RO
6
TJDIS PHS0,RW
5
EXCECM PHS0,RW
4 PAD_DIS2 PHS0,RW
3 CRC_DIS2 PHS0,RW
Description
Reserved
Transmit Jabber Disable
When set, the transmit Jabber Timer (2048 bytes) is disabled. Otherwise it is Enable
Excessive Collision Mode Control : 0:aborts this packet when excessive collision
counts more than 15, 1: still tries to transmit this packet
PAD Appends Disable for Packet Index 2
CRC Appends Disable for Packet Index 2
Preliminary
17
Version: DM9010-17--DS-P04
Jan. 18, 2006
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