DM9010 View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
DM9010
Davicom Semiconductor, Inc.
'DM9010' PDF : 61 Pages View PDF
DM9010
Single Chip Ethernet Controller with General Processor Interface
0
FLCE HPS0,RW Flow Control Enable
Set to enable the flow control mode (i.e. to disable TX function)
6.12 EEPROM & PHY Control Register ( 0BH )
Bit
Name
Default
Description
7:6 RESERVED 0,RO Reserved
5
REEP PH0,RW Reload EEPROM. Driver needs to clear it up after the operation completes
4
WEP
PH0,RW Write EEPROM Enable
3
EPOS PH0,RW EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
2
ERPRR PH0,RW EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
1
ERPRW PH0,RW EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.
0
ERRE
PH0,RO EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress
6.13 EEPROM & PHY Address Register ( 0CH )
Bit
Name
Default
Description
7:6 PHY_ADR PH01,RW PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 if
internal PHY is selected
5:0
EROA PH0,RW EEPROM Word Address or PHY Register Address
6.14 EEPROM & PHY Data Register (EE_PHY_L：0DH EE_PHY_H：0EH)
Bit
Name
Default
Description
7:0 EE_PHY_L PH0,RW EEPROM or PHY Low Byte Data
This data is made to write low byte of word address defined in Reg. CH to
EEPROM or PHY
7:0 EE_PHY_H PH0,RW EEPROM or PHY High Byte Data
This data is made to write high byte of word address defined in Reg. CH to
EEPROM or PHY
6.15 Wake Up Control Register ( 0FH )
Bit
Name
Type
Description
7:6 RESERVED 0,RO Reserved
5
LINKEN
P0,RW When set, it enables Link Status Change Wake up Event
This bit will not be affected after software reset
4 SAMPLEEN P0,RW When set, it enables Sample Frame Wake up Event
This bit will not be affected after software reset
3 MAGICEN P0,RW When set, it enables Magic Packet Wake up Event
This bit will not be affected after software reset
2
LINKST
P0,RO When set, it indicates that Link Change and Link Status Change Event occurred
This bit will not be affected after software reset
1 SAMPLEST P0,RO When set, it indicates that the sample frame is received and Sample Frame Event
occurred. This bit will not be affected after software reset
0
MAGICST
P0,RO When set, indicates the Magic Packet is received and Magic packet Event
Preliminary
21
Version: DM9010-17--DS-P04
Jan. 18, 2006
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