DM9010 View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
DM9010
Davicom Semiconductor, Inc.
'DM9010' PDF : 61 Pages View PDF
DM9010
Single Chip Ethernet Controller with General Processor Interface
4
ONEPM PH0,RW One Packet Mode
When set, only one packet transmit command can be issued before transmit
completed.
When cleared, at most two packet transmit command can be issued before
transmit completed.
3~0
IFGS
PH0,RW Inter-Frame Gap Setting
0XXX: 96-bit
1000: 64-bit
1001: 72-bit
1010:80-bit
1011:88-bit
1100:96-bit
1101:104-bit
1110: 112-bit
1111:120-bit
6.26 Operation Test Control Register ( 2EH )
Bit
Name
Default
Description
7~6
SCC
PH0,RW System Clock Control
Set the internal system clock.
00: 50Mhz
01: 20MHz
10: 100MHz
11:1KHz
In external MII mode, only internal system clock is always 50Mhz.
5
EXTMII PH0,RW Force to External MII mode
4
SOE
PH0,RW SRAM Output-Enable Always ON
3
SCS
PH0,RW SRAM Chip-Select Always ON
2~0
PHYOP PH0,RW PHY operation mode
6.27 Special Mode Control Register ( 2FH )
Bit
Name
Default
7
SM_EN HPS0,RW Special Mode Enable
6~3 RESERVED HPS0,RO Reserved
2
FLC
HPS0,RW Force Late Collision
1
FB1
HPS0,RW Force Longest Back-off time
0
FB0
HPS0,RW Force Shortest Back-off time
Description
6.28 Early Transmit Control/Status Register ( 30H )
Bit
Name
Default
Description
7
ETE
HPS0, RW Early Transmit Enable
Enable bits[1:0]
6
ETS2
HPS0,RO Early Transmit Status II (underrun)
5
ETS1
HPS0,RO Early Transmit Status I (underrun)
4~2 RESERVED 000,RO Reserved
Preliminary
24
Version: DM9010-17--DS-P04
Jan. 18, 2006
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