DM9010 View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
DM9010
Davicom Semiconductor, Inc.
'DM9010' PDF : 61 Pages View PDF
DM9010
Single Chip Ethernet Controller with General Processor Interface
6.37 INT Pin Control Register ( 39H )
Bit
Name
Default
7:2 Reserved PS0,RO Reserved
INT Pin Output Type Control
1
INT_TYPE PET0,RW 1: INT Open-Collector output
0: INT direct output
INT Pin Polarity Control
0
INT_POL PET0,RW 1: INT active low
0: INT active high
Description
6.38 Monitor Register 1 ( 40H )
Bit
Name
Default
7
BWIDTH T0,RO
6
DWIDTH T0,RO
5
INTOC
ET0,RO
4
INTP
ET0,RO
3
IO16OC
E0,RO
2
IO16P
E0,RO
1
ILEDM
ET0,RO
0
MDIX
ET0,RO
8-bit Data Strap Latch Status
32-bit Data Strap Latch Status
INT Open-Collect Pin Status
INT Polarity Pin Status
IO16/32 Open-Collect Pin Status
IO16/32 Polarity Pin Status
LED Mode Status
MDIX Strap Pin Status
Description
6.39 Monitor Register 2 ( 41H )
Bit
Name
Default
7~4 RESERVED 0,RO
3
NOEEP
T0,RO
2
EXTMII
T0,RO
1
PHYUP
T0,RO
0
RMII
T0,RO
Description
Reserved
NO Load EEPROM Strap Pin Status
External MII Strap Pin Status
PHY Power-Up Strap Pin Status
Reverse MII strap Pin Status
6.40 System Clock Turn ON Control Register ( 50H )
Bit
Name
Default
Description
7:1 Reserved
-
Reserved
Stop Internal System Clock
0
DIS_CLK
P0,W 1: internal system clock turn off, internal PHYceiver also power down
0: internal system clock is ON
6.41 Resume System Clock Control Register ( 51H )
When the INDEX port set to 51H, the internal system clock is turn ON.
6.42 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H)
Bit
Name
Default
Description
7:0 MRCMDX X,RO Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged. And the DM9010 starts to pre-fetch the SRAM data
to internal data buffers.
Preliminary
27
Version: DM9010-17--DS-P04
Jan. 18, 2006
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