DM9010 View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
DM9010
Davicom Semiconductor, Inc.
'DM9010' PDF : 61 Pages View PDF
DM9010
Single Chip Ethernet Controller with General Processor Interface
7:6 IOMODE
T0, RO
Bit 7 Bit 6
0 0 16-bit mode
0 1 32-bit mode
1 0 8-bit mode
1 1 Reserved
5
LNKCHG PHS0,RW/C1 Link Status Change
4
UDRUN PHS0,RW/C1 Transmit Underrun
3
ROO
PHS0,RW/C1 Receive Overflow Counter Overflow
2
ROS
PHS0,RW/C1 Receive Overflow
1
PT
PHS0,RW/C1 Packet Transmitted
0
PR
PHS0,RW/C1 Packet Received
6.51 Interrupt Mask Register (FFH)
Bit
Name
Default
7
PAR
HPS0,RW
6 RESERVED
RO
5
LNKCHGI PHS0,RW
4
UDRUNI PHS0,RW
3
ROOI
PHS0,RW
2
ROI
PHS0,RW
1
PTI
PHS0,RW
0
PRI
PHS0,RW
Description
Enable the SRAM read/write pointer to automatically return to the start address
when pointer addresses are over the SRAM size. Driver needs to set. When
driver sets this bit, REG_F5 will set to 0Ch automatically
Reserved
Enable Link Status Change Interrupt
Enable Transmit Underrun Interrupt
Enable Receive Overflow Counter Overflow Interrupt
Enable Receive Overflow Interrupt
Enable Packet Transmitted Interrupt
Enable Packet Received Interrupt
Preliminary
29
Version: DM9010-17--DS-P04
Jan. 18, 2006
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