DM9010
Single Chip Ethernet Controller with General Processor Interface
1~0
ETT
HPS0,RW Early Transmit Threshold
Start transmit when data write to TX FIFO reach the byte-count threshold
Bit-1 bit-0
----- ----
00
01
10
11
threshold
-------------
: 12.5%
: 25%
: 50%
: 75%
6.29 Transmit Check Sum Control Register ( 31H )
Bit
Name
Default
Description
7~3 RESERVED 0,RO Reserved
2
UDPCSE HPS0,RW UDP CheckSum Generation Enable
1
TCPCSE HPS0,RW TCP CheckSum Generation Enable
0
IPCSE
HPS0,RW IP CheckSum Generation Enable
6.30 Receive Check Sum Control Status Register ( 32H )
Bit
Name
Default
Description
7
UDPS HPS0,RO UDP CheckSum Status
0: checksum OK, if UDP packet
6
TCPS HPS0,RO TCP CheckSum Status
0: checksum OK, if TCP packet
5
IPS
HPS0,RO IP CheckSum Status
0: checksum OK, if IP packet
4
UDPP HPS0,RO UDP Packet
3
TCPP HPS0,RO TCP Packet
2
IPP
HPS0,RO IP Packet
1
RCSEN HPS0,R Receive CheckSum Checking Enable
W
When set, the checksum status will store in packet first byte of status header.
0
DCSE
HPS0,R Discard CheckSum Error Packet
W
When set, if IP/TCP/UDP checksum field is error, this packet will be discarded.
6.31 External PHYceiver Address Register ( 33H )
Bit
Name
Default
Description
7
ADR_EN HPS0,R External PHY Address Enabled
W
When set in external MII mode, the external PHYceiver address is defined at bit
4~0.
6~5 Reserved HPS0,RO Reserved
4~0 EPHYADR HPS01,R External PHY Address Bit 4~0
W
The PHY address in external MII mode.
6.32 General Purpose Control Register 2 ( 34H )
Bit
Name
Default
Description
Preliminary
25
Version: DM9010-17--DS-P04
Jan. 18, 2006