DM9010
Single Chip Ethernet Controller with General Processor Interface
occurred. This bit will not be affected after a software reset
6.16 Physical Address Register ( 10H~15H )
Bit
Name
Default
7:0
PAB5
E,RW Physical Address Byte 5 (15H)
7:0
PAB4
E,RW Physical Address Byte 4 (14H)
7:0
PAB3
E,RW Physical Address Byte 3 (13H)
7:0
PAB2
E,RW Physical Address Byte 2 (12H)
7:0
PAB1
E,RW Physical Address Byte 1 (11H)
7:0
PAB0
E,RW Physical Address Byte 0 (10H)
Description
6.17 Multicast Address Register ( 16H~1DH )
Bit
Name
Default
7:0
MAB7
X,RW Multicast Address Byte 7
7:0
MAB6
X,RW Multicast Address Byte 6
7:0
MAB5
X,RW Multicast Address Byte 5
7:0
MAB4
X,RW Multicast Address Byte 4
7:0
MAB3
X,RW Multicast Address Byte 3
7:0
MAB2
X,RW Multicast Address Byte 2
7:0
MAB1
X,RW Multicast Address Byte 1
7:0
MAB0
X,RW Multicast Address Byte 0
(1DH)
(1CH)
(1BH)
(1AH)
(19H)
(18H)
(17H)
(16H)
Description
6.18 General purpose control Register ( 1EH )
Bit
Name
Default
Description
7 RESERVED 0,RO Reserved
6:4
GPC64
PH, General Purpose Control 6~4
111,RO Define the input/output direction of pins GPIO6~4 respectively.
These bits are all forced to “1”s, so pins GPIO6~4 are output only.
3:1
GPC31
PH, General Purpose Control 3~1
000,RW Define the input/output direction of pins GPIO 3~1 respectively.
When a bit is set 1, the direction of correspondent bit of General Purpose Register
is output. Other defaults are input
0
GPC0
PH1,RO General Purpose Control 0
This bit define the input/output direction of pin GPIO0.
These bits are forced to “1”, so pin GPIO0 is output only.
Pin GPIO0 is forced to output for internal PHYceiver power down function.
6.19 General purpose Register ( 1FH )
Bit
Name
Default
Description
7 RESERVED 0,RO Reserved
6:4 GEPIO6-4 PH0,RW General Purpose Data 6~4
These bits are reflect to pin GEPIO6~4 respectively.
3:1 GEPIO3-1 PH0,RW General Purpose 3~1
When the correspondent bit of General Purpose Control Register is 1, the value of
the bit is reflected to pin GEPIO3-1
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit to be read is reflected from correspondent pins of GEPIO3-1
The GEPIOs are mapped to pins GEPIO3 to GEPIO1 respectively
Preliminary
22
Version: DM9010-17--DS-P04
Jan. 18, 2006