DM9010 View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
DM9010
Davicom Semiconductor, Inc.
'DM9010' PDF : 61 Pages View PDF
DM9010
Single Chip Ethernet Controller with General Processor Interface
0
GEPIO0 ET1,RW General Purpose 0
The value of the bit is the output to pin GEPIO0
This bit also defines the power down status of Internal PHYceiver. Driver needs to
clear this bit by writing “0” when it wants internal PHYceiver to be power up. This
default value can be programmed by strap pin GPIO4 or EEPROM. Please refer to
the EEPROM description
6.20 TX SRAM Read Pointer Address Register (22H~23H)
Bit
Name
Default
Description
7:0 TRPAH PS0,RO TX SRAM Read Pointer Address High Byte (23H)
7:0 TRPAL PS0.RO TX SRAM Read Pointer Address Low Byte (22H)
6.21 RX SRAM Write Pointer Address Register (24H~25H)
Bit
Name
Default
Description
7:0 RWPAH PS,0CH,RO RX SRAM Write Pointer Address High Byte (25H)
7:0 RWPAL PS,04H.RO RX SRAM Write Pointer Address Low Byte (24H)
6.22 Vendor ID Register (28H~29H)
Bit
Name
Default
7:0
VIDH PHE,0AH,RO Vendor ID High Byte (29H)
7:0
VIDL PHE,46H.RO Vendor ID Low Byte (28H)
Description
6.23 Product ID Register (2AH~2BH)
Bit
Name
Default
7:0
PIDH PHE,90H,RO Product ID High Byte (2BH)
7:0
PIDL PHE,00H.RO Product ID Low Byte (2AH)
Description
6.24 Chip Revision Register (2CH)
Bit
Name
Default
7:0
CHIPR
19H,RO CHIP Revision
Description
6.25 Transmit Control Register 2 ( 2DH )
Bit
Name
Default
Description
7
LED
PH0,RW Led Mode
When set, the LED pins act as led mode 1.
When cleared, the led mode is depending on strap pin or EEPROM setting.
6
RLCP
PH0,RW Retry Late_Collision Packet
Re-transmit the packet with late-collision
5
DTU
PH0,RW Disable TX Underrun Retry
Disable to re-transmit the underruned packet
Preliminary
23
Version: DM9010-17--DS-P04
Jan. 18, 2006
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