DM9010 View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
DM9010
Davicom Semiconductor, Inc.
'DM9010' PDF : 61 Pages View PDF
DM9010
Single Chip Ethernet Controller with General Processor Interface
2 PAD_DIS1 PHS0,RW PAD Appends Disable for Packet Index 1
1 CRC_DIS1 PHS0,RW CRC Appends Disable for Packet Index 1
0
TXREQ PHS0,RW TX Request. Auto clears after sending completely
6.4 TX Status Register I ( 03H ) for packet index I
Bit
Name
Default
Description
7
TJTO
PHS0,RO Transmit Jabber Time Out
It is set to indicate that the transmitted frame is truncated due to more than 2048
bytes are transmitted
6
LC
PHS0,RO Loss of Carrier
It is set to indicate the loss of carrier during the frame transmission. It is not valid in
internal Loopback mode
5
NC
PHS0,RO No Carrier
It is set to indicate that there is no carrier signal during the frame transmission. It is
not valid in internal Loopback mode
4
LC
PHS0,RO Late Collision
It is set when a collision occurs after the collision window of 64 bytes
3
COL
PHS0,RO Collision Packet
It is set to indicate that the collision occurs during transmission
2
EC
PHS0,RO Excessive Collision
It is set to indicate that the transmission is aborted due to 16 excessive collisions
1:0 RESERVED 0,RO Reserved
6.5 TX Status Register II ( 04H ) for packet index I I
Bit
Name
Default
Description
7
TJTO
PHS0,RO Transmit Jabber Time Out
It is set to indicate that the transmitted frame is truncated due to more than 2048
bytes are transmitted
6
LC
PHS0,RO Loss of Carrier
It is set to indicate the loss of carrier during the frame transmission. It is not valid in
internal Loopback mode
5
NC
PHS0,RO No Carrier
It is set to indicate that there is no carrier signal during the frame transmission. It is
not valid in internal Loopback mode
4
LC
PHS0,RO Late Collision
It is set when a collision occurs after the collision window of 64 bytes
3
COL
PHS0,RO Collision packet, collision occurs during transmission
2
EC
PHS0,RO Excessive Collision
It is set to indicate that the transmission is aborted due to 16 excessive collisions
1:0 RESERVED 0,RO Reserved
6.6 RX Control Register ( 05H )
Bit
Name
Default
7 HASHALL PHS0,RW
6
WTDIS PHS0,RW
5 DIS_LONG PHS0,RW
Description
Filter All address in Hash Table
Watchdog Timer Disable
When set, the Watchdog Timer (2048 bytes) is disabled. Otherwise it is enabled
Discard Long Packet
Packet length is over 1522byte
Preliminary
18
Version: DM9010-17--DS-P04
Jan. 18, 2006
Share Link: 