EDI9LC644V2012BC View Datasheet(PDF) - White Electronic Designs Corporation

Part Name

Description

MFG CO.

EDI9LC644V2012BC

128Kx32 SSRAM/1Mx32 SDRAM

White Electronic Designs Corporation 

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EDI9LC644V

FIG. 7 SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4

NOTES:

1. Minimum row cycle times are required to complete internal DRAM operation.

2 Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will

be Hi-Z (tSHZ) after the clock.

3. Access time from Row active command. tCC *(tRCD + CAS Latency - 1) + tSAC.

4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)

White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

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