EDI9LC644V2012BC View Datasheet(PDF) - White Electronic Designs Corporation
Part Name
Description
MFG CO.
'EDI9LC644V2012BC' PDF : 25 Pages View PDF
EDI9LC644V
FIG. 9 SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
NOTES:
1. SDCE can be “don’t care” when SDRAS, SDCAS and SDWE are high at the clock going high edge.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
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