EDI9LC644V2012BC View Datasheet(PDF) - White Electronic Designs Corporation
Part Name
Description
MFG CO.
'EDI9LC644V2012BC' PDF : 25 Pages View PDF
EDI9LC644V
FIG. 8 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
NOTES:
1. To write data before burst read ends. BWE should be asserted three cycle prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.
3. BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge
cycle will be masked internally.
15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
Share Link: 
