EVAL-ADUM4160EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADUM4160EBZ' PDF : 16 Pages View PDF
ADuM3160
COMPATIBILITY OF UPSTREAM APPLICATIONS
The ADuM3160 is designed specifically for isolating a USB
peripheral. However, the chip has two USB interfaces that meet
the electrical requirements for driving USB cables. This opens the
possibility of implementing isolation in downstream USB ports
such as isolated cables, which have generic connections to both
upstream and downstream devices, as well as isolating host ports.
In a fully compliant application, a downstream-facing port must
be able to detect whether a peripheral is low speed or full speed
based on the application of the upstream pull-up. The buffers
and logic conventions must adjust to match the requested speed.
Because the ADuM3160 sets its speed by hardwiring pins, the
part cannot adjust to different peripherals on the fly.
The practical result of using the ADuM3160 in a host port is
that the port works at a single speed. This behavior is acceptable
in embedded host applications; however, this type of interface is
not fully compliant as a general-purpose USB port.
Isolated cable applications have a similar issue. The cable operates
at the preset speed only; therefore, treat cable assemblies as custom
applications, not general-purpose isolated cables.
POWER SUPPLY OPTIONS
In most USB transceivers, 3.3 V is derived from the 5 V USB bus
through an LDO regulator. The ADuM3160 includes internal
LDO regulators on both the upstream and downstream sides. The
output of the LDO regulators is available on the VDD1 and VDD2 pins.
In some cases, especially on the peripheral side of the isolation,
there may not be a 5 V power supply available. The ADuM3160
has the ability to bypass the regulator and run on a 3.3 V supply
directly.
Two power pins are present on each side, VBUSx and VDDx. If 5 V
is supplied to VBUSx, an internal regulator creates 3.3 V to power
the xD+ and xD− drivers. VDDx provides external access to the
3.3 V supply to allow external bypass as well as bias for external
pull-ups. If only 3.3 V is available, it can be supplied to both VBUSx
and VDDx. This disables the regulator and powers the coupler
directly from the 3.3 V supply.
Figure 5 shows how to configure a typical application when the
upstream side of the coupler receives power directly from the USB
bus and the downstream side receives 3.3 V from the peripheral
power supply. The downstream side can run from a 5 V VBUS2
power supply as well. It can be connected in the same manner
as VBUS1, as shown in Figure 5, if needed.
Data Sheet
PRINTED CIRCUIT BOARD LAYOUT
The ADuM3160 digital isolator requires no external interface
circuitry for the logic interfaces. For full speed operation, the D+
and D− lines on each side of the device require a 24 Ω ± 1% series
termination resistor. These resistors are not required for low speed
applications. Power supply bypassing is required at the input and
output supply pins (see Figure 5). Install bypass capacitors between
VBUSx and VDDx on each side of the chip. The capacitors should have
a minimum value of 0.1 µF and low ESR. The total lead length
between both ends of the capacitor and the power supply pin
should not exceed 10 mm.
Bypassing between Pin 2 and Pin 8 and between Pin 9 and Pin 15
should also be considered unless the ground pair on each package
side is connected close to the package. All logic level signals are
3.3 V and should be referenced to the local VDDx pin or 3.3 V logic
signals from an external source.
VBUS1 = 5.0V INPUT
VDD1 = 3.3V OUTPUT
VBUS2 = 3.3V INPUT
VDD2 = 3.3V INPUT
VBUS1
GND1
VDD1
VBUS2
GND2
VDD2
PDEN
SPU
ADuM3160
SPD
PIN
UD–
DD–
UD+
DD+
GND1
GND2
Figure 5. Suggested PCB Layout Example
In applications that involve high common-mode transients, care
should be taken to minimize board coupling across the isolation
barrier. Furthermore, design the board layout such that any coupling
that does occur affects all pins equally on a given component side.
Failure to ensure this can cause voltage differentials between pins
that exceed the absolute maximum ratings of the device, thereby
leading to latch-up or permanent damage.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by the
pulses, indicating input logic transitions.
The limitation on the magnetic field immunity of the ADuM3160
is set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this may occur. The 3 V operating condition of the
ADuM3160 is examined because it represents the most suscep-
tible mode of operation.
Rev. C | Page 10 of 16
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