EVAL-ADUM4160EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADUM4160EBZ' PDF : 16 Pages View PDF
Data Sheet
ADuM3160
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
4.5 V ≤ VBUS1 ≤ 5.5 V, 4.5 V ≤ VBUS2 ≤ 5.5 V; 3.1 V ≤ VDD1 ≤ 3.6 V, 3.1 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over
the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. All
voltages are relative to their respective grounds.
Table 1.
Parameter
Symbol Min
Typ
Max Unit Test Conditions/Comments1
DC SPECIFICATIONS
Total Supply Current2
1.5 Mbps
750 kHz logic signal rate, CL = 450 pF
VDD1 or VBUS1 Supply Current
IDD1 (L)
5
7
mA
VDD2 or VBUS2 Supply Current
IDD2 (L)
5
7
mA
12 Mbps
6 MHz logic signal rate, CL = 50 pF
VDD1 or VBUS1 Supply Current
IDD1 (F)
6
8
mA
VDD2 or VBUS2 Supply Current
IDD2 (F)
6
8
mA
Idle Current
VDD1 or VBUS1 Idle Current
IDD1 (I)
1.7
2.3
mA
Input Currents
IDD−, IDD+, −1
IUD+, IUD−,
ISPD, IPIN,
ISPU, IPDEN
+0.1 +1
µA
0 V ≤ VDD−, VDD+, VUD+, VUD−, VSPD, VPIN,
VSPU, VPDEN ≤ 3.0 V
Single-Ended Logic High Input Threshold
VIH
2.0
V
Single-Ended Logic Low Input Threshold
VIL
0.8
V
Single-Ended Input Hysteresis
VHST
0.4
V
Differential Input Sensitivity
VDI
0.2
V
|VXD+ − VXD−|
Logic High Output Voltages
VOH
2.8
3.6
V
RL = 15 kΩ, VL = 0 V
Logic Low Output Voltages
VOL
0
0.3
V
RL = 1.5 kΩ, VL = 3.6 V
VDD1 and VDD2 Supply Undervoltage Lockout
VUVLO
2.4
3.1
V
VBUS1 Supply Undervoltage Lockout
VUVLOB1
3.5
4.35 V
VBUS2 Supply Undervoltage Lockout
VUVLOB2
3.5
4.4
V
Transceiver Capacitance
CIN
10
pF
UD+, UD−, DD+, DD− to ground
Capacitance Matching
10
%
Full Speed Driver Impedance
ZOUTH
4
20
Ω
Impedance Matching
10
%
SWITCHING SPECIFICATIONS, I/O PINS,
LOW SPEED
Low Speed Data Rate
Propagation Delay3
tPHL, tPLH
1.5
Mbps CL = 50 pF
325
ns
CL = 50 pF, SPD = SPU = low,
VDD1, VDD2 = 3.3 V
Side 1 Output Rise/Fall Time (10% to 90%),
Low Speed
tRL, tFL
75
300
ns
CL = 450 pF, SPD = SPU = low,
VDD1, VDD2 = 3.3 V
Low Speed Differential Jitter, Next Transition |tLJN|
45
ns
CL = 50 pF
Low Speed Differential Jitter, Paired Transition |tLJP|
15
ns
CL = 50 pF
SWITCHING SPECIFICATIONS, I/O PINS,
FULL SPEED
Maximum Data Rate
Propagation Delay3
12
Mbps CL = 50 pF
tPHL, tPLH 20
60
70
ns
CL = 50 pF, SPD = SPU = high,
VDD1, VDD2 = 3.3 V
Output Rise/Fall Time (10% to 90%), Full Speed tRF, tFF
4
20
ns
CL = 50 pF, SPD = SPU = high,
VDD1, VDD2 = 3.3 V
Full Speed Differential Jitter, Next Transition
|tHJN|
3
ns
CL = 50 pF
Full Speed Differential Jitter, Paired Transition |tHJP|
1
ns
CL = 50 pF
Rev. C | Page 3 of 16
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