HT48C10 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48C10' PDF : 59 Pages View PDF
HT48CXX/HT48RXX
TO PD
RESET Conditions
1
u
WDT time-out during normal
operation
1
1 WDT wake-up HALT
Note: “u” means “unchanged”
To guarantee that the system oscillator is
started and stabilized, the SST (System Start-
up Timer) provides an extra-delay. The extra-
delay delays 1024 system clock pulses when the
system powers up or awakes from the HALT
state.
When the system power-up occurs, the SST de-
lay is added during the reset period. But when
the reset comes from the RES pin, the SST delay
is disabled. Any wake-up from HALT will enable
the SST delay.
The status of the chip reset of the functional
units are as shown.
PC
000H
Interrupt
Disabled
Prescaler
Cleared
WDT
Cleared
After a master reset,
WDT begins counting.
Timer/event
counter (0/1)
Input/output ports
Off
Input mode
SP
Point to the top of the
stack
Timer/event counter
There are two timer/event counters imple-
mented in the four microcontrollers. Of the four
microcontrollers, the timer/event counter of the
HT48C10/HT48C30 contains an 8-bit program-
mable count-up counter. On the other hand, the
timer/event counter of the HT48C50/HT48C70
composes of two counters, namely timer/event
counter 0 and timer/event counter 1. The
timer/event counter 0 contains a 16-bit pro-
grammable counter, and the timer/event
counter 1 contains an 8-bit programmable
count-up counter of the HT48C50. The
timer/event counters 0 and 1 of the HT48C70
both contain a 16-bit programmable count-up
counter. The source of the clock of the four mi-
crocontrollers may come from an external
source or the system clock divided by 4. If the
internal instruction clock is applied, only one
reference time-base is available. The external
clock input, on the other hand, allows the user
to count external events, measure time inter-
vals or pulse width, or generate an accurate
time base.
Of the HT48C10/HT48C30, there are two regis-
ters related to the timer/event counter, i.e.,
TMR ([0DH]) and TMRC ([0EH]). There are two
physical registers mapped to the TMR location.
Writing TMR puts the starting value in the
timer/event counter preload register while
reading TMR gets the contents of the timer/
event counter. The TMRC, on the other hand, is
a timer/event counter control register.
Timer/event counter 0/1
23
25th May ’99
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