HT48C10 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48C10' PDF : 59 Pages View PDF
HT48CXX/HT48RXX
Of the HT48C50/HT48C70, the timer/event
counter is comprised by two counters, i.e.,
timer/event counter 0 and timer/event counter
1. There are three registers related to the
timer/event counter 0, namely TMR0H (0CH),
TMR0L (0DH), and TMR0C (0EH). Writing
TMR0L only writes the data into a low byte
buffer, but writing TMR0H writes the data
along with the contents of the low byte buffer
into the timer/event counter 0 preload register
(16-bit). The timer/event counter 0 preload reg-
ister is changed by writing the TMR0H opera-
tions, and writing TMR0L keeps the timer/
event counter 0 preload register unaltered.
Also, reading the TMR0H latches the TMR0L
into the low byte buffer in order to avoid the
false timing problem. Then, reading the TMR0L
will return the contents of the low byte buffer.
In other words, the low byte of the timer/event
counter 0 cannot be read directly. Instead it has
to read the TMR0H first in order to make the
low byte contents of the timer/event counter 0
latched into the buffer. On the other hand, there
are also three registers related to the
timer/event counter 1, namely TMR1H (0FH),
TMR1L (10H), and TMR1C (11H). The timer/
event counter 1 operates in the same manner as
the timer/event counter 0.
The TMR0C is a timer/event counter 0 control
register defining the timer/event counter 0 op-
tions. The timer/event counter 1 has the same
options as the timer/event counter 0 and is de-
fined by TMR1C.
The timer/event counter control registers of the
four microcontrollers are all used to define the
operation mode, counting enable or disable, and
active edge.
The TM0 and TM1 bits define the operation
mode. The event count mode is used to count
external events, which means that the clock
source comes from an external pin TMR of the
HT48C10/HT48C30 or TMR0/TMR1 of the
HT48C50/HT48C70. The timer mode functions
as a normal timer with the clock source coming
from the instruction clock. The pulse width
measurement mode can be used to count the
high or low level duration of the external signal
TMR of the HT48C10/HT48C30 or TMR0/TMR
1 of the HT48C50/HT48C70. The counting is
based on the instruction clock.
In the event count or timer mode, once the
timer/event counter starts counting, it will count
from the current contents in the timer/event
counter to FFH of the HT48C10/HT48C30/
HT48C50 (TMR1) or to FFFFH of the HT48C50
(TMR0)/HT48C70. If an overflow occurs, the
counter is reloaded from the timer/ event counter
preload register and generates the corresponding
interrupt request flag TF (bit 5 of INTC) of the
HT48C10/HT48C30 or T0F/T1F (bit 5/6 of INTC)
of the HT48C50/ HT48C70 at the same time.
Label
Bits
Function
—
0~2 Unused bits, read as “0”
TE
TON
3
To define TMR0/TMR1 active edge of the timer/event counter
(0= active on low to high; 1= active on high to low)
4
To enable/disable timer counting
(0= disabled; 1= enabled)
—
5 Unused bits, read as “0”
TM0
TM1
To define the operating mode
6
7
01= Event count mode (external clock)
10= Timer mode (internal clock)
11= Pulse width measurement mode
00= Unused
TMR0C/TMR1C register
25
25th May ’99
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