HT48C10 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48C10' PDF : 59 Pages View PDF
HT48CXX/HT48RXX
bidirectional input/output lines, labeled from
PA to PD, which are mapped to the [12H], [14H],
[16H], or 18H], respectively. Finally, the
HT48C70 contains 56 bidirectional input/out-
put lines, labeled from PA to PG, which are
mapped to the RAM of [12H], [14H], [16H],
[18H], [1AH], [1CH], and [1EH], respectively. Of
the four microcontrollers, all of these I/O ports
can be used for input and output operations. For
the input operation, these ports are non-latch-
ing, i.e., the inputs should be ready at the T2
rising edge of the instruction MOV A,[m]
(m=12H, 14H, 16H, 18H, 1AH, 1CH, or 1EH).
For the output operation, all data are latched
and remain unchanged until the output latch is
rewritten.
Each I/O line has its own control register (PAC,
PBC, PCC, PDC, PEC, PFC, PGC (the fist three
registers PAC, PBC, PCC are all used by the
four microcontrollers; the register PDC is extra-
used by the HT48C50; all the seven registers
are applied in the HT48C70) to control the in-
put/ output configuration. With this control reg-
ister, CMOS output or schmitt trigger input
with or without pull-high resistor (by mask op-
tion) structures can be reconfigured dynami-
cally (i.e., on-the-fly) under software control. To
function as an input, the corresponding latch of
the control register must be written with a “1”.
The pull-high resistance shows itself automat-
ically if the pull-high option is selected. The
input source(s) also depends on the control reg-
ister. If the value of the control register bit is “1”,
the input will read the pad state. But if the
value of the control register bit is “0”, the con-
tents of the latches will be moved to the internal
bus. The latter is possible in “read-modify-
write” instruction. For the output function,
CMOS is the only configuration. These control
registers are mapped to locations 13H, 15H,
17H, 19H, 1BH, 1DH and 1FH (the first three
locations 13H, 15H, 17H exist in the four micro-
controllers; the location 19H is used for the
HT48C50; all the 7 locations are applied in the
HT48C70).
After a chip reset, these input/output lines stay at
the high level or floating (by mask option). Each
bit of these input/output latches can be set or
cleared by the SET [m].i or CLR [m].i (m=12H,
14H, 16H, 18H, 1AH, 1CH or 1EH (the first
three options, namely 12H, 14H, and 16H, exist
in the four microcontrollers; the HT48C50 is
provided with an extra option of 18H; these
seven options all exist in the HT48C70) instruc-
tion.
Some instructions first input data and then fol-
low the output operations. For example, the
SET [m].i, CLR [m].i, CPL [m] and CPLA [m]
instructions read the entire port states into the
CPU, execute the defined operations (bit-opera-
tion), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability to wake-up
the device.
Mask option
The following table illustrates the five kinds of
mask option provided. All these options have to
be defined to ensure proper system functioning.
No.
Mask Option
OSC type selection. This option is to
decide if an RC or Crystal oscillator is
1
chosen as system clock. If the Crystal
oscillator is selected, the XST (Crystal
Start-up Timer) default is activated;
otherwise the XST is disabled.
WDT source selection. There are three
2 types of selection: on-chip RC oscillator,
instruction clock or disable the WDT.
CLRWDT times selection. This option
defines the way of clearing the WDT by
instruction. “Once” means that the CLR
3 WDT instruction can clear the WDT.
“Twice” means only if both of the CLR
WDT1 and CLR WDT2 instructions have
been executed, the WDT can be cleared.
Wake-up selection. This option defines
the activity of the wake-up function.
4 External I/O pins (PA only) all have the
capability to wake-up the chip from a
HALT.
27
25th May ’99
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