HT48R065G View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48R065G' PDF : 126 Pages View PDF
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Timer Control Registers - TMR0C, TMR1C
The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in
three different modes, the options of which are determined by the contents of their respective control
register.
The Timer Control Register is known as TMRnC. It is the Timer Control Register together with its
corresponding timer register that control the full operation of the Timer/Event Counter. Before the
timer can be used, it is essential that the Timer Control Register is fully programmed with the right data
to ensure its correct operation, a process that is normally carried out during program initialisation.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event
counting mode or the pulse width capture mode, bits 7 and 6 of the Timer Control Register, which are
known as the bit pair TnM1/TnM0, must be set to the required logic levels. The timer-on bit, which is
bit 4 of the Timer Control Register and known as TnON, provides the basic on/off control of the
respective timer. Setting the bit high allows the counter to run, clearing the bit stops the counter. Bits
0~2 of the Timer Control Register determine the division ratio of the input clock prescaler. The
prescaler bit settings have no effect if an external clock source is used. If the timer is in the event count
or pulse width capture mode, the active transition edge level type is selected by the logic level of bit 3
of the Timer Control Register which is known as TnEG. The TnS bit selects the internal clock source if
used.
TMR0C Register
Bit
Name
R/W
POR
7
T0M1
R/W
0
6
T0M0
R/W
0
5
T0S
R/W
0
4
T0ON
R/W
0
3
T0EG
R/W
1
2
T0PSC2
R/W
0
1
T0PSC1
R/W
0
0
T0PSC0
R/W
0
Bit 7,6
Bit 5
Bit 4
Bit 3
Bit 2~0
T0M1, T0M0: Timer0 operation mode selection
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
T0S: timer clock source
0: fSYS
1: LXT oscillator
T0S selects the clock source for fTP which is provided for Timer 0, the Time-Base and
the PWM. If the PWM is enabled, then fSYS will be selected, overriding the T0S selection.
T0ON: Timer/event counter counting enable
0: disable
1: enable
T0EG:
Event counter active edge selection
0: count on raising edge
1: count on falling edge
Pulse Width Capture active edge selection
0: start counting on falling edge, stop on rasing edge
1: start counting on raising edge, stop on falling edge
T0PSC2, T0PSC1, T0PSC0: Timer prescaler rate selection
Timer internal clock=
000: fTP
001: fTP/2
010: fTP/4
011: fTP/8
100: fTP/16
101: fTP/32
110: fTP/64
111: fTP/128
Rev. 1.10
59
October 23, 2012
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