HT48R065G View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48R065G' PDF : 126 Pages View PDF
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
TMR1C Register
Bit
7
6
5
4
3
2
1
0
Name
T1M1
T1M0
T1S
T1ON
T1EG
¾
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
¾
¾
¾
POR
0
0
0
0
1
¾
¾
¾
Bit 7,6
Bit 5
Bit 4
Bit 3
Bit 2~0
T1M1, T1M0: Timer 1 Operation mode selection
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
T1S: timer clock source
0: fSYS/4
1: LXT oscillator
T1ON: Timer/event counter counting enable
0: disable
1: enable
T1EG:
Event counter active edge selection
0: count on raising edge
1: count on falling edge
Pulse Width Capture active edge selection
0: start counting on falling edge, stop on rasing edge
1: start counting on raising edge, stop on falling edge
unimplemented, read as ²0²
Timer Mode
In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing an
internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the
Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct
value as shown.
Control Register Operating Mode
Select Bits for the Timer Mode
Bit7
Bit6
1
0
In this mode the internal clock is used as the timer clock. The timer input clock source is fSYS, fSYS/4 or
the LXT oscillator depending upon whether the Timer/Event Counter 0 or Timer/Event Counter 1 is
selected. For Timer/Event Counter 0, the timer clock source is further divided by a prescaler, the value
of which is determined by the bits T0PSC2~T0PSC0 in the Timer Control Register TMR0C. The
timer-on bit, TnON must be set high to enable the timer to run. Each time an internal clock high to low
transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal
is generated and the timer will reload the value already loaded into the preload register and continue
counting. A timer overflow condition and corresponding internal interrupt is one of the wake-up
sources, however, the internal interrupts can be disabled by ensuring that the TnE bits of the INTC0
register are reset to zero.
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
Timer Mode Timing Chart
T im e r + N
T im e r + N + 1
Rev. 1.10
60
October 23, 2012
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