HT49CA1 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT49CA1' PDF : 58 Pages View PDF
HT49RA1/HT49CA1
Timer/Event Counter 0/1 Registers -
TMR0, TMR0C, TMR1H, TMR1L, TMR1C
All devices possess a single internal 8-bit count-up
timer. An associated register known as TMR0 is the lo-
cation where the timer¢s 8-bit value is located. This reg-
ister can also be preloaded with fixed data to allow
different time intervals to be setup. An associated con-
trol register, known as TMR0C, contains the setup infor-
mation for this timer, which determines in what mode the
timer is to be used as well as containing the timer on/off
control function.
All devices possess a single internal 16-bit count-up
timer. An associated register known as TMR1H, TMR1L
is the location where the timer¢s 16-bit value is located.
This register can also be preloaded with fixed data to al-
low different time intervals to be setup. An associated
control register, known as TMR1C, contains the setup
information for this timer, which determines in what
mode the timer is to be used as well as containing the
timer on/off control function.
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA, PB, PC and PD. These
labeled I/O registers are mapped to specific addresses
within the Data Memory as shown in the Data Memory
table, which are used to transfer the appropriate output
or input data on that port. One flexible feature of these
registers is the ability to directly program single bits us-
ing the ²SET [m].i² and ²CLR [m].i² instructions. The PC
port also has a control register known as PCC, and has
the ability to change its I/O pin from output to input and
vice versa by manipulating the bit in the register.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. Although Port B remains fixed as an input
only port, all pins on Port A, Port C and Port D, have the
ability to function as either input or output.
The device provides 13 bidirectional input/output lines
and 8 input lines. The I/O Ports are known as Port A,
D a ta B u s
W r ite
C h ip R e s e t
D
Q
CK Q
S
V DD
W eak
P u ll- u p
R e a d I/O
PA, PD Input/Output Ports
P A 0~P A 7
P D 0~P D 3
Port C and Port D and the input Port is known as Port B.
These ports are mapped to the Data Memory with spe-
cific addresses as shown in the Special Purpose Data
Memory table. The Port A and Port D I/O ports can be
used for both input and output operations, however, it
must be noted that unlike Port C, they do not have port
control registers. Setting up an PA or PD port pin as an
input is achieved by first setting its output high which ef-
fectively places its NMOS output transistor in a high im-
pedance state allowing the pin to be now used as an
input.
For input operation, these ports are non-latching, which
means the inputs must be ready at the T2 rising edge of
instruction ²MOV A,[m]², where m denotes the port ad-
dress. For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an exter-
nal resistor. To eliminate the need for these external re-
sistors, all pins on Port A, Port B and Port D have a
permanently connected pull high resistor. The pull high
resistor on Port C is chosen via a configuration option.
These pull-high resistors are implemented using a weak
PMOS transistor.
Port B Wake-up
The device has a HALT instruction enabling the
microcontroller to enter a Power Down Mode and pre-
serve power, a feature that is important for battery and
other low-power applications. Various methods exist to
wake-up the microcontroller, one of which is to change
the logic condition on one of the Port B pins from high to
low. After a ²HALT² instruction forces the microcontroller
into entering a HALT condition, the processor will re-
main idle or in a low-power state until the logic condition
of the selected wake-up pin on Port B changes from high
to low. This function is especially suitable for applica-
tions that can be woken up via external switches. Note
that each pin on Port B can be selected individually to
have this wake-up feature.
V DD
W eak
P u ll- u p
D a ta B u s
R e a d I/O
S y s te m W a k e -u p
IN T 0 fo r P B 0
IN T 1 fo r P B 1
T M R /T M R 0 fo r P B 2
T M R 1 fo r P B 3
P B 0~P B 7
W a k e - u p O p tio n
PB Input Port
Rev. 1.10
15
March 30, 2014
Share Link: 
