HT49CA1 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT49CA1' PDF : 58 Pages View PDF
b7 b6 b5 b4 b3 b2 b1 b0
40H
SEG 0
41H
SEG 1
HT49RA1/HT49CA1
b7 b6 b5 b4 b3 b2 b1 b0
40H
SEG 0
41H
SEG 1
:U nused
R e a d a s "0 "
5FH
S E G 31
5FH
S E G 31
60H
S E G 32
60H
S E G 32
(1 /2 o r 1 /3 D u ty )
LCD Memory Map
(1 /4 D u ty )
the binary value ²1². After this, the LCD Memory can
then be accessed by using indirect addressing through
the use of Memory Pointer MP1. With Bank 1 selected,
then using MP1 to read or write to the memory area,
40H~60H, depending upon which device is chosen, will
result in operations to the LCD Memory. Directly ad-
dressing the LCD Memory is not applicable and will re-
sult in a data access to the Bank 0 General Purpose
Data Memory.
The accompanying diagrams show the LCD Memory
Map for the 33´2, 33´3 or 32´4 format pixel drive capa-
bility. The 4-COM format will be automatically setup if
the 1/4 duty configuration option is selected while the
3-COM format will be automatically setup if the 1/2 or
1/3 duty configuration option is selected.
LCD Control Register - LCDC
The device contains a single register known as, LCDC,
which is used to control some internal LCD driver func-
tions. The LCDEN bit is the overall on/off control for the
LCD driver and can be used to power down the driver
and thus used to conserve power when the LCD is not
used. As four segment lines are also pin-shared with
four Port PD lines, bits SEGPT0~SEGPT3 in the LCDC
register are used to determine which function is chosen,
either LCD segment line or normal I/O line.
LCD Clock
The LCD clock is driven by the internal clock source fS,
which can originate from either the WDT oscillator, the
RTC oscillator or fSYS/4, the choice of which is deter-
mined by a configuration option. For proper LCD opera-
tion, this fS internal clock source then passes through a
divider, to provide an LCD clock source frequency as
near as possible to 4kHz.
fS Clock Source
WDT Oscillator
RTC Oscillator
fSYS/4
LCD Clock Selection
WDT/22
RTC/23
~ f S Y S / 4
22
fS Y S /4
28
LCD Clock Frequency Selection
The available division ratios, however, depends on the
clock source that is used for the internal clock source, fS.
If the clock source for fS originates from the WDT oscilla-
tor, then only a fixed division ratio of fS/22 is available. If
the clock source for fS originates from the RTC oscilla-
tor, then only one division ratio of fS/23 is available. How-
ever, if the clock source for fS originates from fSYS/4,
then a range of LCD clock frequencies are available
from fS/22 to fS/28, the value of which is selected by a fur-
ther available configuration option. These ratios ensure
that for proper LCD operation, a signal frequency as
near as possible to 4kHz, can be selected. For an LCD
clock frequency of 4kHz, the microcontroller LCD driver
circuitry will generate an LCD frame frequency between
55Hz and 62Hz. This is in line with the general LCD op-
erating frequency range which lies between 25Hz and
250Hz. Note that if the selected LCD clock frequency is
too high, this will result in a higher than required frame
frequency and give rise to higher power consumption
while selecting a too low frequency may result in flicker.
It is therefore important that if fSYS/4 is used as the clock
source for fS, the correct configuration option should be
chosen to obtain an LCD clock frequency as close to
4kHz as possible.
Rev. 1.10
18
March 30, 2014
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