HT49CA1 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT49CA1' PDF : 58 Pages View PDF
HT49RA1/HT49CA1
When using the pin as an output, its logic level can be
setup by loading byte wide data into the appropriate port
register or by programming individual bits in these regis-
ters, using the ²SET [m].i² and ²CLR [m].i² instructions.
Note that when using these bit control instructions, a
read-modify-write operation takes place. The
microcontroller must first read in the data on the entire
port, modify it to the required new bit values and then re-
write this data back to the output ports. However, in the
case of NMOS type pins, there are some special consid-
erations that must be noted. In the case of an NMOS pin
that is set high by the microcontroller, i.e. placed into a
high impedance condition, but driven low by externally
connected circuitry, this pin would be read as being in a
low condition during the read phase of the ²SET [m].i
and ²CLR [m].i² instructions. When the ensuing write
phase occurs, this pin, having been read as being in a
low condition during the read phase, would then be con-
sequently erroneously set low. For this reason great
care must be taken when using these bit control instruc-
tions with NMOS output types.
Port B has the additional capability of providing wake-up
functions. When the device is in the Power Down Mode,
various methods are available to wake the device up.
One of these is a high to low transition of any of the Port
B pins. Single or multiple pins on Port B can be setup to
have this function.
Liquid Crystal Display (LCD) Driver
For large volume applications, which incorporate an
LCD in their design, the use of a custom display rather
than a more expensive character based display reduces
costs significantly. However, the corresponding signals
required, which vary in both amplitude and time, to drive
such a custom display require many special consider-
ations for proper LCD operation to occur. This device in-
cludes internal LCD signal generating circuitry and
various configuration options, which will automatically
generate these time and amplitude varying signals to
provide a means of direct driving and easy interfacing to
a range of custom LCDs.
LCD Memory
The device provides a specific area of Data Memory for
the LCD data. This data area is known as the LCD Mem-
ory. Any data written here will be automatically read by
the internal LCD driver circuits, which will in turn auto-
matically generate the necessary LCD driving signals.
Therefore any data written into the LCD Memory will be
immediately reflected into the actual LCD display con-
nected to the microcontroller. The start address of the
LCD Memory is 40H, the end address of the LCD Mem-
ory is 60H.
As the LCD Data Memory addresses overlap those of
the General Purpose Data Memory, the LCD Data Mem-
ory is stored in its own memory data bank, which is dif-
ferent from that of the General Purpose Data Memory.
The LCD Data Memory is stored in Bank 1. The Data
Memory Bank is chosen by using the Bank Pointer,
which is a special function register in the Data Memory,
with the name, BP. When the lowest bit of the Bank
Pointer have the binary value ²0², only the General Pur-
pose Data Memory will be accessed, no read or write
actions to the LCD Memory will take place. To access
the LCD Memory therefore requires first that Bank 1 is
selected by setting the lowest bit of the Bank Pointer to
b7
SEG PT3 SEG PT2 SEG PT1 SEG PT0
b0
L C D E N R T C E N L C D C R e g is te r
R T C O s c illa to r E n a b le
1 : e n a b le
0 : d is a b le
L C D E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
S E G 0 /P D 0 p in fu n c tio n
1:P D 0
0:S E G 0
S E G 1 /P D 1 p in fu n c tio n
1:P D 1
0:S E G 1
S E G 2 /P D 2 p in fu n c tio n
1:P D 2
0:S E G 2
LCD Control Register - LCDC
S E G 3 /P D 3 p in fu n c tio n
1:P D 3
0:S E G 3
Rev. 1.10
17
March 30, 2014
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