HT66F016 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F016' PDF : 116 Pages View PDF
HT66F016/HT66F017/HT68F016/HT68F017
HT66F016R/HT66F017R/HT68F016R/HT68F017R
Compact Type TM Operating Modes
The Compact Type TM can operate in one of three oper-
ating modes, Compare Match Output Mode, PWM
Mode or Timer/Counter Mode. The operating mode is
selected using the TnM1 and TnM0 bits in the TMnC1
register.
Compare Match Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1
register, should be set to 00B respectively. In this mode
once the counter is enabled and running it can be
cleared by three methods. These are a counter over-
flow, a compare match from Comparator A and a com-
pare match from Comparator P. When the TnCCLR bit is
low, there are two ways in which the counter can be
cleared. One is when a compare match occurs from
Comparator P, the other is when the CCRP bits are all
zero which allows the counter to overflow. Here both
TnAF and TnPF interrupt request flags for the Compara-
tor A and Comparator P respectively, will both be gener-
ated.
If the TnCCLR bit in the TMnC1 register is high then the
counter will be cleared when a compare match occurs
from Comparator A. However, here only the TnAF inter-
rupt request flag will be generated even if the value of
the CCRP bits is less than that of the CCRA registers.
Therefore when TnCCLR is high no TnPF interrupt re-
quest flag will be generated. If the CCRA bits are all
zero, the counter will overflow when its reaches its maxi-
mum 16-bit, FFFF Hex, value, however here the TnAF
interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison
is made, the TM output pin will change state. The TM
output pin condition however only changes state when a
TnAF interrupt request flag is generated after a compare
match occurs from Comparator A. The TnPF interrupt
request flag, generated from a compare match occurs
from Comparator P, will have no effect on the TM output
pin. The way in which the TM output pin changes state
are determined by the condition of the TnIO1 and TnIO0
bits in the TMnC1 register. The TM output pin can be se-
lected using the TnIO1 and TnIO0 bits to go high, to go
low or to toggle from its present condition when a com-
pare match occurs from Comparator A. The initial condi-
tion of the TM output pin, which is setup after the TnON
bit changes from low to high, is setup using the TnOC
bit. Note that if the TnIO1 and TnIO0 bits are zero then
no pin change will take place.
Counter Value Counter overflow
CCRP=0
CCRP > 0
TnCCLR = 0; TnM [1:0] = 00
Counter cleared by CCRP value
0xFFFF
CCRP
CCRA
CCRP > 0
Resume
Pause
Counter
Restart
Stop
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
Time
TM O/P Pin
Output pin set to
initial Level Low
if TnOC=0
Output Toggle with
TnAF flag
Here TnIO [1:0] = 11
Toggle Output select
Output not affected by TnAF
flag. Remains High until reset
by TnON bit
Output Inverts
when TnPOL is high
Output Pin
Note TnIO [1:0] = 10
Reset to Initial value
Active High Output select
Output controlled by
other pin-shared function
Compare Match Output Mode -- TnCCLR = 0
Note: 1. With TnCCLR=0, a Comparator P match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
Rev. 1.40
58
November 22, 2016
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