HT66F016 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F016' PDF : 116 Pages View PDF
HT66F016/HT66F017/HT68F016/HT68F017
HT66F016R/HT66F017R/HT68F016R/HT68F017R
Timer/Counter Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1
register should be set to 11 respectively. The
Timer/Counter Mode operates in an identical way to the
Compare Match Output Mode generating the same in-
terrupt flags. The exception is that in the Timer/Counter
Mode the TM output pin is not used. Therefore the
above description and Timing Diagrams for the Com-
pare Match Output Mode can be used to understand its
function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other
pin-shared function.
PWM Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1
register should be set to 10 respectively. The PWM func-
tion within the TM is useful for applications which require
functions such as motor control, heating control, illumi-
nation control etc. By providing a signal of fixed fre-
quency but of varying duty cycle on the TM output pin, a
square wave AC waveform can be generated with vary-
ing equivalent DC RMS values.
As both the period and duty cycle of the PWM waveform
can be controlled, the choice of generated waveform is
extremely flexible. In the PWM mode, the TnCCLR bit
has no effect on the PWM operation. Both of the CCRA
and CCRP registers are used to generate the PWM
waveform, one register is used to clear the internal
counter and thus control the PWM waveform frequency,
while the other one is used to control the duty cycle.
Which register is used to control either frequency or duty
cycle is determined using the TnDPX bit in the TMnC1
register. The PWM waveform frequency and duty cycle
can therefore be controlled by the values in the CCRA
and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP,
will be generated when a compare match occurs from
either Comparator A or Comparator P. The TnOC bit in
the TMnC1 register is used to select the required polar-
ity of the PWM waveform while the two TnIO1 and
TnIO0 bits are used to enable the PWM output or to
force the TM output pin to a fixed high or low level. The
TnPOL bit is used to reverse the polarity of the PWM
output waveform.
Counter Value
CCRP
CCRA
Counter cleared
by CCRP
TnDPX = 0; TnM [1:0] = 10
Counter Reset when
TnON returns high
Pause Resume
Counter Stop if
TnON bit low
TnON
Time
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM Mode -- TnDPX = 0
PWM resumes
operation
Output controlled by
other pin-shared function
Output Inverts
when TnPOL = 1
Note:
1. Here TnDPX=0 -- Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
Rev. 1.40
60
November 22, 2016
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