HT66F25D View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F25D' PDF : 177 Pages View PDF
A/D Flash Type 8-bit MCU with EEPROM
HT66F24D/HT66F25D
IDLE0 Mode
The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the WDTC register is low. In the IDLE0 Mode the
system oscillator will be inhibited from driving the CPU but some peripheral functions will remain
operational such as the Watchdog Timer, TMs and SIM. In the IDLE0 Mode, the system oscillator
will be stopped. In the IDLE0 Mode the Watchdog Timer clock, fS, will either be on or off depending
upon the fS clock source. If the source is fSYS/4, then the fS clock will be off, and if the source comes
from fSUB then fS will be on.
IDLE1 Mode
The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the WDTC register is high. In the IDLE1 Mode the
system oscillator will be inhibited from driving the CPU but may continue to provide a clock source
to keep some peripheral functions operational such as the Watchdog Timer, TMs and SIM. In the
IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high
speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, fS, will be on.
If the source is fSYS/4, then the fS clock will be on, and if the source comes from fSUB then fS will be
on.
Control Register
The corresponding system control registers, SMOD and CTRL, are used for overall control of the
internal clocks within the device.
SMOD Register
Bit
7
6
5
4
3
Name CKS2 CKS1 CKS0 FSTEN LTO
R/W
R/W
R/W
R/W
R/W
R
POR
0
0
0
0
0
2
HTO
R
0
1
IDLEN
R/W
1
0
HLCLK
R/W
1
Bit 7~5
Bit 4
CKS2~CKS0: The system clock selection when HLCLK is 0
000: fSUB (fLXT or fLIRC)
001: fSUB (fLXT or fLIRC)
010: fH/64
011: fH/32
100: fH/16
101: fH/8
110: fH/4
111: fH/2
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source, which is the LIRC, a divided version of the high
speed system oscillator can also be chosen as the system clock source.
FSTEN: Fast Wake-up Control (only for HXT)
0: Disable
1: Enable
This is the Fast Wake-up Control bit which determines if the fSUB clock source is
initially used after the device wakes up. When the bit is high, the fSUB clock source can
be used as a temporary system clock to provide a faster wake up time as the fSUB clock
is available.
Rev. 1.10
42
March 25, 2013
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