HT66F25D View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F25D' PDF : 177 Pages View PDF
A/D Flash Type 8-bit MCU with EEPROM
HT66F24D/HT66F25D
SLOW Mode to NORMAL Mode Switching
In SLOW Mode the system uses the LIRC low speed system oscillator. To switch back to the
NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to 1
or HLCLK bit is 0 but CKS2~CKS0 is set to 010B, 011B, 100B, 101B, 110B or 111B. As a certain
amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit
is checked. The amount of time required for high speed system oscillator stabilization depends upon
which high speed system oscillator type is used.
S LO W M ode
C K S 2~C K S 0¹000B ,001B as H LC LK =0
orH LC LK =1
N O R M A L M ode
W D T a n d L V D a r e a ll o ff
ID L E N = 0
H A L T in s tr u c tio n is e x e c u te d
S LE E P 0 M ode
W D T o r L V D is o n
ID L E N = 0
H A L T in s tr u c tio n is e x e c u te d
S LE E P 1 M ode
ID L E N = 1 , F S Y S O N = 0
H A L T in s tr u c tio n is e x e c u te d
ID L E 0 M o d e
ID L E N = 1 , F S Y S O N = 1
H A L T in s tr u c tio n is e x e c u te d
ID L E 1 M o d e
Entering the SLEEP0 Mode
There is only one way for the device to enter the SLEEP0 Mode and that is to execute the HALT
instruction in the application program with the IDLEN bit in SMOD register equal to 0 and the
WDT and LVD both off. When this instruction is executed under the conditions described above, the
following will occur:
• The system clock, WDT clock and Time Base clock will be stopped and the application program
will stop at the HALT instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and stopped.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Rev. 1.10
47
March 25, 2013
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